NDLI: A noise and signal integrity verification flow for hierarchical design

Content Provider	IEEE Xplore Digital Library
Author	Mohamed, S.A. Manaf, A.A. Teh Chih Chiang
Copyright Year	2011
Description	Author affiliation: Electrical Engineering Dept., Universiti Sains Malaysia (USM), Penang, Malaysia (Mohamed, S.A.; Manaf, A.A.) \|\| Intel Microelectronic Sdn Bhd, Penang, Malaysia (Teh Chih Chiang)
Abstract	Hierarchical design spans the complete framework of a design flow from RTL, synthesis, place and route, timing closure and various other analyses before signoff. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key issue for Deep Sub-Micron design. This paper discusses how to analyze, avoid and suggest a proper solution to deal with signal integrity effect in a hierarchical design. The intention is to ensure that a complex design can be delivered to the market with accurate, fast and trusted analysis and sign-off solution. Main proposed approach is to analyze a 45nm process technology hierarchical design using Primetime-SI. Signal integrity effects in the design are explored thoroughly to guarantee any recommendation made to reduce and repair the signal integrity effects is suitable and appropriate. Case study presented demonstrates the proposed methodology has provided valuable and useful perimeter to overcome signal integrity caveats in hierarchical design.
Starting Page	250
Ending Page	255
File Size	632818
Page Count	6
File Format	PDF
ISBN	9781457720581
e-ISBN	9781457720598
DOI	10.1109/ICCAIE.2011.6162140
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-04
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Couplings Crosstalk noise Delta delay Noise Crosstalk Maintenance engineering Delay Optimization Signal integrity Aggressor Victim
Content Type	Text
Resource Type	Article

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