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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xing-yuan Li Fang Ji |
| Copyright Year | 2013 |
| Description | Author affiliation: Coll. of Software, Beijing Univ. of Technol., Beijing, China (Xing-yuan Li) || Coll. of Comput. Sci., Beijing Univ. of Technol., Beijing, China (Fang Ji) |
| Abstract | The h.264 standard adopts an effective intra-frame prediction coding algorithm to reduce spatial redundancies and improve the compression ratio, but this high performance was reached by exhaustively trying all available prediction modes and selecting the best one, which becomes the bottleneck of this algorithm. In this paper, we propose a high throughput prediction and mode decision architecture to lessen the impact of this part to the h.264 coder. The architecture was described in Verilog HDL and synthesized to Xilinx Spartan6 FPGA, the results show it gets higher throughput when compared with related work. |
| Sponsorship | Hubei Univ. Automot. Technol. |
| Starting Page | 1611 |
| Ending Page | 1615 |
| File Size | 607755 |
| Page Count | 5 |
| File Format | |
| ISBN | 9780769550046 |
| DOI | 10.1109/ICCIS.2013.422 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-06-21 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Video coding FPGA H.264 Computer architecture Encoding Discrete cosine transforms Mode decision Intra-frame prediction Field programmable gate arrays Clocks |
| Content Type | Text |
| Resource Type | Article |
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