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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Su Bo Wang Zhiying Huang Libo Shi Wei Wang Yourui |
| Copyright Year | 2012 |
| Abstract | With the expanding of large computing platforms and the increasing of on chip transistors, power consumption becomes a significant problem. Many methods are proposed in different design levels to solve the problem. In this paper, we introduce asynchronous technique to an IEEE-754 double-precision floating-point multiplier aiming to reduce its power consumption. The control path of the asynchronous multiplier employs redundant four-phase latch controllers and asymmetric delay elements. Experimental results show the power consumption of the asynchronous multiplier is at least 16% lower than its synchronous equivalent when running the PARSEC benchmarks. After synthesized in UMC 180nm technology, the area overhead of the asynchronous multiplier is 0.31%. |
| Starting Page | 1360 |
| Ending Page | 1363 |
| File Size | 224438 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467324069 |
| DOI | 10.1109/ICCIS.2012.216 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-08-17 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Power demand Latches Asynchronous Pipelines Floating-point Benchmark testing Multiplier Throughput Low-power Delay Asynchronous circuits |
| Content Type | Text |
| Resource Type | Article |
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