NDLI: Low complexity SDR transceiver design using Simulink, Matlab and Xilinx

Content Provider	IEEE Xplore Digital Library
Author	Hassan, H. Yahaya, C.K.H.C.K. Ahmad, N. Bakhtir, N.I.S.
Copyright Year	2012
Description	Author affiliation: Science & Technology Research Institute of Defense, (STRIDE), Kompleks Induk STRIDE, 43000 Kajang, Selangor, Malaysia (Bakhtir, N.I.S.) \|\| Faculty of Electrical Engineering, Universiti Teknologi MARA, 40450 Shah Alam, Selangor, Malaysia (Hassan, H.; Yahaya, C.K.H.C.K.; Ahmad, N.)
Abstract	The revolution of modern radio communication application such as radar, electronic warfare and signal intelligence using SDR technology has open an interest among researchers to adopt the technology in wireless communication system. This paper is focused on mechanisms and methodology to implement a low complexity SDR transceiver using Simulink, Matlab and Xilinx for FPGA environment. In this design, a spectrum frequency between 5 MHz to 20 MHz is sampled using QPSK modulation technique to achieve encoding and decoding of IF signal. The mechanisms and methodology of proposed transceiver design would help in SDR designing by providing a fast way altering a system with low complexity. It also opens the possibility of integrating cognitive radio aspect into wireless networks such as 3G and 4G in the future.
Starting Page	55
Ending Page	60
File Size	396843
Page Count	6
File Format	PDF
ISBN	9781467348294
e-ISBN	9781467348287
e-ISBN	9781467348270
DOI	10.1109/ICTC.2012.6386779
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-15
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless communication Phase shift keying Field Programmable Gate Array (FPGA) Software packages Software Defined Radio (SDR) Quadrature Phase-Shift Keying (QPSK) Digital signal processing Receivers Intermediate Frequency (IF) Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in