NDLI: Power- and performance-aware fine-grained reconfigurable router architecture for NoC

Content Provider	IEEE Xplore Digital Library
Author	Mondal, H.K. Gade, S.H. Kishore, R. Deb, S.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Commun. Eng., Indraprastha Inst. of Inf. Technol., Delhi, New Delhi, India (Mondal, H.K.; Gade, S.H.; Kishore, R.; Deb, S.)
Abstract	Networks-on-Chip (NoCs) have been well accepted for energy efficient on-chip communications for multicore systems. But, a NoC router consumes considerable leakage power even when not in use. For large scale systems, number of unused routers at any time is reasonably high. A significant amount of this leakage power can be saved by applying fine-grained power-gating to unused routers in a NoC. In this paper, we propose fine-grained reconfigurable router architecture (FGRRA) for energy efficient on-chip communications. We also propose strategies to avoid situations where power-gated routers (PGRs) block forward path during packet transfer or isolate a destination router. This is achieved by using additional channels referred as non-blocking bypass channels (NBBC). We evaluate our proposed router design in presence of real and synthetic traffic patterns. FGRRA saves up to 88.76% of leakage power with 2.42% area overhead as compared with baseline router. Based on the utilization, FGRRA also reduces the total network power consumption by 36.18% on average without significant performance degradation. Design considerations for augmenting existing power-gated routers with this technique and corresponding overheads are also presented.
Starting Page	1
Ending Page	6
File Size	433023
Page Count	6
File Format	PDF
e-ISBN	9781509001729
DOI	10.1109/IGCC.2015.7393682
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Low power design Pipelines Computer architecture Logic gates Routing Energy efficiency System-on-chip Energy-efficient on-chip communication Power-gating
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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