NDLI: Improving linearity in class-AB power amplifiers using a body-biased NMOS predistortion stage

Content Provider	IEEE Xplore Digital Library
Author	Rashtian, H. Mirabbasi, S.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada (Rashtian, H.; Mirabbasi, S.)
Abstract	A technique for improving the linearity of CMOS class-AB power amplifiers (PAs) is introduced. The technique is based on compensating for the voltage-dependent nonlinear gate-source capacitance of the input transistor of the PA. This compensation is achieved through using an NMOS capacitor, i.e., an NMOS transistor with its source and drain shorted, as a predistortion stage. To enhance cancellation of the nonlinearity, body biasing is incorporated as an additional control scheme into the predistortion stage. As a proof-of-concept, a 2.4-GHz class-AB power amplifier with the proposed predistortion stage has been designed and laid out in a 0.13-μm CMOS technology. Post-layout simulation results show that the third-order input-referred intercept point (IIP3) of the designed PA improves by more than 3-dB when the bulk voltage of the predistortion device is biased appropriately. The PA achieves unsaturated output power of +20 dBm while drawing 125 mA from a 1.2 V supply voltage.
Starting Page	1
Ending Page	6
File Size	641264
Page Count	6
File Format	PDF
ISBN	9781479906239
DOI	10.1109/IGCC.2013.6604480
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET CMOS PA Linearity Logic gates Capacitance Class-AB Predistortion Threshold voltage Body biasing Power amplifier
Content Type	Text
Resource Type	Article

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