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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ting An Hao Cai de Barros Naviner, L.A. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. Commun. et Electron., Inst. Mines-Telecom, Paris, France (Ting An; Hao Cai; de Barros Naviner, L.A.) |
| Abstract | Hot carrier injection (HCI) and negative bias temperature instability (NBTI) become dominant reliability issues in nanometer CMOS technology. These aging effects can induce additional delay which will be accumulated through logic gates and thus degrade the performance of the circuits. This paper discusses performance degradations induced by aging mechanisms in digital integrated circuits. We propose an aging-aware synthesis flow taking into account NBTI and HCI. This flow is demonstrated through the implementation of several architectures of adders using CMOS technology. The simulation results show that Kogge-Stone Adder (KSA) and SKlansky Adder (SKA) are the best solutions whether in terms of the complexity or the resistance to aging effects with induced delay degradation below 0.35%. |
| Starting Page | 51 |
| Ending Page | 55 |
| File Size | 1533309 |
| Page Count | 5 |
| File Format | |
| e-ISBN | 9789532330779 |
| DOI | 10.1109/MIPRO.2014.6859531 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-05-26 |
| Publisher Place | Croatia |
| Access Restriction | Subscribed |
| Rights Holder | MIPRO |
| Subject Keyword | Human computer interaction Degradation Aging Delays CMOS integrated circuits Reliability Adders |
| Content Type | Text |
| Resource Type | Article |
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