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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Printz, H. Stubley, P. |
| Copyright Year | 1993 |
| Description | Author affiliation: Digital Equipment Corp., Paris Res. Lab., Rueil-Malmaison, France (Printz, H.) |
| Abstract | The design and performance of a nonadaptive hardware system for data compression by arithmetic coding are presented. The alphabet of the data source is the full 256-symbol ASCII character set, plus a non-ASCII end-of-file symbol. The key ideas are the non-arithmetic representation of the current interval width, which yields improved coding efficiency in the interval width update, and the design of a circuit for the code point update, which operates at a high speed independent of the length of the code point register. On a reconfigurable coprocessor, constructed from commercially available field-programmable gate arrays and static RAM, implementation compresses its input stream at better than 16 MBytes/sec.< |
| Starting Page | 128 |
| Ending Page | 137 |
| File Size | 630739 |
| Page Count | 10 |
| File Format | |
| ISBN | 0818633921 |
| DOI | 10.1109/DCC.1993.253137 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1993-03-30 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Digital arithmetic Laboratories Data compression Coprocessors Field programmable gate arrays Difference equations Registers Circuit testing System testing |
| Content Type | Text |
| Resource Type | Article |
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