NDLI: A novel low cost, high performance and reliable silicon interposer

Content Provider	IEEE Xplore Digital Library
Author	Yazdani, F.
Copyright Year	2015
Description	Author affiliation: BroadPak Corp., San Jose, CA, USA (Yazdani, F.)
Abstract	Silicon interposer has emerged as a substrate of choice for integrating fine pitch, high density devices. Conventional packaging of 2.5D/3D devices involves multiple level of assemblies. Normally, 2.5D/3D devices are first assembled on thinned silicon interposer with aspect ratio of 10:100 followed by second level assembly on a multi-layer organic build-up substrate. In this study we introduce direct assembly of silicon interposer on PCB, resulting in reduced cost and increased performance for 2.5D/3D applications as well as wafer-level fan-out applications. We investigate effect of under-fill on solder joint reliability during direct assembly of silicon interposer on PCB. A $10×10mm^{2}$ interposer test vehicle was designed and fabricated on 310um thick rigid silicon substrate. BGA of side of the interposer was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a $50×50mm^{2}$ FR-4 PCB through a reflow process. We present cost analysis, design flow, and direct assembly of rigid silicon interposer on PCB. Effect of under-fill on the solder joint reliability is demonstrated using CSAM images during temperature cycles at 250, 500, 750 and 1000 intervals. It is shown that all samples successfully passed the temperature cycle stress test.
Starting Page	1
Ending Page	6
File Size	1672569
Page Count	6
File Format	PDF
e-ISBN	9781479986828
DOI	10.1109/CICC.2015.7338400
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Assembly Substrates Reliability Copper Packaging Yield 2.5D/3D Cost Design Flip Chip Integration Package Silicon Interposer Substrate Thermal Stress TSV Underfill Warpage
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Assembly process development of 2.5D integration for high performance processer

Assembly of large dies fine pitch Cu/low-k FCBGA package with through silicon via (TSV) interposer

3D fracture mechanics analysis of underfill delamination for flip chip packages

3D FRACTURE MECHANICS ANALYSIS OF UNDERFILL DELAMINATION FOR FLIP CHIP PACKAGES

Effect of substrate warpage on flip chip BGA thermal stress simulation

Reliability Evaluation of Warpage of Flip Chip Package with Some Kinds of Underfill Material

Design, simulation, and process development for 2.5D TSV interposer for high performance processer packaging

Mitigation of warpage for large 2.5D Through Silicon Interposer (TSI) package assembly

Warpage behavior in 2.5D package using Si-interposer

A novel low cost, high performance and reliable silicon interposer

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