NDLI: A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing

Content Provider	IEEE Xplore Digital Library
Author	Hyo-Eun Kim Jun-Seok Park Jae-Sung Yoon Seok-Hoon Kim Lee-Sup Kim
Copyright Year	2012
Description	Author affiliation: System LSI, Samsung Electronics, Giheung, Korea (Jae-Sung Yoon; Seok-Hoon Kim) \|\| Department of Electrical Engineering, KAIST, Daejeon, Korea (Hyo-Eun Kim; Jun-Seok Park; Lee-Sup Kim)
Abstract	A unified media application processor (UMAP) with a low-power mixed-mode feature extraction engine (FEE) is presented for 2D/3D image analysis/synthesis applications on handheld devices. UMAP supports not only graphics and vision for augmented reality (AR) but also 3D reconstruction and 3D display for 3D-view AR based on heterogeneous many-core platform. A frame-level 3-stage pipelined architecture enables real-time (50fps in VGA) performance in 3D-view AR, while a mixed-mode FEE dynamically saves active power by reconfiguring operation modes between analog and digital processing. Especially for low power operation in media processing, four pairs of analog current contention logics (CCL) are implemented in FEE. The implemented CCL does not require digital-to-analog or analog-to-digital converters (DAC/ADC) in interfacing digital and analog domains. It includes a diode-connected sensing stabilizer which reduces minimum sensing current. Therefore, average power consumed in CCL is reduced by 44.9%. In the implemented UMAP, the proposed FEE replaces the parallel processing core cluster in the analog processing mode, as a result, 96.5% of cluster power and 99.1% of target detection time are saved. The dynamic mode transition between analog and digital processing based on run-time tracking of region-of-interest (ROI) reduces system energy dissipation by up to 84.2% compared to the state-of-the-art embedded media processors.
Starting Page	1
Ending Page	4
File Size	1294228
Page Count	4
File Format	PDF
ISBN	9781467315555
ISSN	08865930
e-ISBN	9781467315562
e-ISBN	9781467315548
DOI	10.1109/CICC.2012.6330650
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Feature extraction Graphics Media Engines Three dimensional displays Hardware Estimation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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