NDLI: Impedance, filtering and noise in n-phase passive CMOS mixers

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2015 IEEE Custom Integrated Circuits Conference (CICC)

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Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

Table of contents

Educational session 1

Welcome message

A quantization noise cancelling fractional-N type ΔΣ frequency synthesizer using SAR-based DAC gain calibration

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

A 0.6V 2.2mW 58-to-73GHz divide-by-4 injection-locked frequency divider

A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz

A distributed “hybrid” wave oscillator array for millimeter-wave phased-arrays

A 57.5-to-90.1GHz magnetically-tuned multi-mode CMOS VCO

A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation

PLLs, VCOs, and dividers

A feedback controlled coil driver for transcutaneous power transmission

A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy

A 46 μW motion artifact reduction bio-signal sensor with ICA based adaptive DC level control for sleep monitoring system

A 695 pW standby power optical wake-up receiver for wireless sensor nodes

A 180nm CMOS image sensor with on-chip optoelectronic image compression

Design of a monolithic CMOS image sensor integrated focal plane wire-grid polarizer filter mosaic

Biomedical and sensors

A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion

A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibration

A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control

A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization

Problem of timing mismatch in interleaved ADCs

High-speed data converters

22-nm fully-depleted tri-gate CMOS transistors

Reliability challenges for the continued scaling of IC technologies

Extremely thin SOI for system-on-chip applications

Present and future applications of Silicon Carbide devices and circuits

Advanced IC technologies I

Phase Change Memory: Scaling and applications

A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technology

A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode

An energy efficient 32nm 20 MB L3 cache for $Intel^{®}$ $Xeon^{®}$ processor E5 family

Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS

Advanced memory topics

Flexible solar-energy harvesting system on plastic with thin-film LC oscillators operating above ft for inductively-coupled power delivery

Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems

EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS

Fully integrated capacitive converter with all digital ripple mitigation

A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 μm CMOS technology

A 0.5V start-up 87% efficiency $0.75mm^{2}$ on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration

Non-load-balance-dependent high efficiency single-inductor multiple-output (SIMO) DC-DC converters

An integrated MESFET voltage follower LDO for high power and PSR RF and analog applications

Power management

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation

Online Reinforcement Learning NoC for portable HD object recognition processor

A 4-bit 12GS/s data acquisition System-on-Chip including a flash ADC and 4-channel DeMUX in 130nm CMOS

A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing

A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS

A low-cost audio computer for information dissemination among illiterate people groups

Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator

Energy-efficient architecture and enabling technology for advanced SOCs

Fully depleted devices for designers: FDSOI and FinFETs

Intel Ivy Bridge unveiled — The first commercial tri-gate, high-k, metal-gate CPU

Lithography and design integration — New paradigm for the technology architecture development

Silicon-based THz circuits, systems and applications

Compact and behavioral modeling of transistors from NVNA measurements: New flows and future trends

True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example

A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation

Slew-aware buffer insertion for through-silicon-via-based 3D ICs

A calibrated pathfinding model for signal integrity analysis on interposer

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Electronic design automation (EDA) solutions for ESD-robust design and verification

Design solutions for 3D integration and signal integrity

A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC

A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS

A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration

A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC

A $0.015mm^{2}$ 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction

A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS

Data converter techniques

Power delivery: Droop, jitter, test and debug story

Behavioral modeling for RF and AMS

A 17pJ/bit 915MHz 8PSK/O-QPSK transmitter for high data rate biomedical applications

CMOS handset power amplifiers: Directions for the future

High power, high efficiency stacked mmWave Class-E-like power amplifiers in 45nm SOI CMOS

A 20 dBm Q-band SiGe Class-E power amplifier with 31% peak PAE

A 1.5GHz 0.2psRMS jitter 1.5mW divider-less FBAR ADPLL in 65nm CMOS

A 2.7GHz 3.9mW Mesh-BJT LC-VCO with −204dBc/Hz FOM in 65nm CMOS

Linearization of class D amplifiers

A CMOS switched-capacitor fractional bandgap reference

Analog Techniques

Large-scale statistical performance modeling of analog and mixed-signal circuits

Designing reliable analog circuits in an unreliable world

Statistical aging under dynamic voltage scaling: A logarithmic model approach

Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables

Impact of subthreshold hump on bulk-bias dependence of offset voltage variability in weak and moderate inversion regions

Modeling & design for variability and reliability

A digital phase-locked loop with calibrated coarse and stochastic fine TDC

A 2.3–4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on

An 8.5–11.5Gbps SONET transceiver with referenceless frequency acquisition

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching

Design of high-speed wireline transceivers for backplane communications in 28nm CMOS

A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS

A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS

A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers

High-speed wireline transceivers and clocking

Clock-gated harmonic rejection mixers

A Full-Band processor for reduction of RF mixer LO harmonic images

An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS

Impedance, filtering and noise in n-phase passive CMOS mixers

A single-chip x-band chirp radar MMIC with stretch processing

A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS

Radio receiver techniques

Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs)

A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integration

$0.61W/mm^{2}$ resonant inductively coupled power transfer for 3D-ICs

Advances in 3D design and optimization

A 150nW, $5ppm/^{o}$ C, 100kHz On-Chip clock source for ultra low power SoCs

An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC

A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOS

A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling

7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage

Design of organic complementary circuits for RFID tags application

Amorphous silicon 5 bit flash analog to digital converter

A custom processor for node and power management of a battery-less body sensor node in 130nm CMOS

A $0.791mm^{2}$ fully on-chip controller with self-error-correction for boost DC-DC converter based on Zero-Order Control

Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology

A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS

28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimization

Field programmable SONOS ESD protection design

Characterization of Inverse Temperature Dependence in logic circuits

Multi-band, multi-mode, low-power CMOS receiver front-end for sub-GHz ISM/SRD band with narrow channel spacing

A digital PLL with two-step closed-locking for multi-mode/multi-band SAW-less transmitter

A supply-voltage scalable, 45 nm CMOS ultra-wideband receiver for mm-wave ranging and communication

A low-power highly multiplexed parallel PRBS generator

FEC-based 4 Gb/s backplane transceiver in 90nm CMOS

A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration

Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors

A wideband ultra-low-current on-chip ammeter

A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation

A 5–300MHz CMOS transceiver for multi-nuclear NMR spectroscopy

A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation

A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application

6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS

Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors

Non-invasion power monitoring with 120% harvesting energy improvement by maximum power extracting control for high sustainability power meter system

A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6

A unified model and direct extraction methodologies of various CPWs for CMOS mm-wave applications

Modeling the response of Bang-Bang digital PLLs to phase error perturbations

A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition

A mixed-mode FPAA SoC for analog-enhanced signal processing

A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS

A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting

A low-phase-noise wide-tuning-range quadrature oscillator in 65nm CMOS

A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection

A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS

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Impedance, filtering and noise in n-phase passive CMOS mixers

Content Provider	IEEE Xplore Digital Library
Author	Molnar, A. Andrews, C.
Copyright Year	2012
Description	Author affiliation: Cornell University, Ithaca, New York, 14853 (Molnar, A.; Andrews, C.)
Abstract	Here we review a simple Linear Time-Invariant (LTI) model that captures the impedance transparency properties of CMOS passive mixers, as well as filtering and noise effects and compare these analyses to measured results. We then extend this model to account for device parameters and suggest a simple metric for predicting limits to performance as a function of process and frequency. Finally we discuss the requirements such mixers place upon the LO circuits, and interactions between such circuits and performance.
Starting Page	1
Ending Page	8
File Size	897553
Page Count	8
File Format	PDF
ISBN	9781467315555
ISSN	08865930
e-ISBN	9781467315562
e-ISBN	9781467315548
DOI	10.1109/CICC.2012.6330616
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mixers Impedance Baseband Radio frequency Noise Harmonic analysis Semiconductor device modeling receiver harmonic rejection mixer multi-phase multiphase clock out-of-band interference passive mixer
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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