NDLI: A High-Throughput Maximum a posteriori Probability Detector

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Table of contents

3D Capacitive Interconnections for High Speed Interchip Communication

Low-Jitter Active Deskewing Through Injection-Locked Resonant Clocking

Wideband Inductive-coupling Interface for High-performance Portable System

A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

A Disturb Decoupled Column Select 8T SRAM Cell

Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM

Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology

Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times

PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs

Charge-Based Compact Modeling of Multiple-Gate MOSFET

Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm Technology

A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling

A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR

A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping DAC

A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications

Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections

Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders

CAD Techniques for Power Optimization in Virtex-5 FPGAs

Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation

Analysis of Data Remanence in a 90nm FPGA

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A Single-Conversion SiGe BiCMOS Satellite TV LNB Front-End Using an Image Reject Mixer and a Calibrated Full-Rate VCO

A Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e)

A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver

Single-Chip UHF RFID reader in 0.18- μm CMOS

A Versatile Integrated Circuit for the Acquisition of Biopotentials

A Spectral-Scanning Magnetic Resonance Imaging (MRI) Integrated System

A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear Model

Multi-functional Monolithic-MEMS Tactile Imager Using Flexible Deformation of Silicon IC

Testing SerDes beyond 4 Gbps - changing priorities

Challenges and Solutions for Standards-Based Serial 10 Gb/s Backplane Ethernet

2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device

Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os

Embedded Test Features for High-Speed Serial I/O

On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Networks

Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter

A 0.18 μm CMOS Capacitive Detection Lab-on-Chip

A 400MHz RF Transceiver for Implantable Biomedical Micro-Stimulators

A Monolithic Bandpass Amplifier for Neural Signal Processing with 25-Hz Low-Frequency Cutoff

A Low Power Carbon Nanotube Chemical Sensor System

A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration

A Fourth Order Elliptic Low-Pass Filter with Wide Range of Programmable Bandwidth, Using Four Identical Integrators

An Idle-Tone Free Dynamic Element Matching Algorithm

A 65-dB DR 1-MHz BW 110-MHz IF bandpass ΣΔ modulator employing electromechanical loop filter

A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain

A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS

A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process

Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability

Rapid Estimation of the Probability of SRAM Failure due to MOS Threshold Variations

A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme

Dynamic Data Stability in Low-power SRAM Design

An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement

Solution to ESD Induced Pocket Isolation Failure in Multi Well CMOS

Integration of CMP Modeling in RC Extraction and Timing Flow

Integrated Inductor Actively Engaging Metal Filling Rules

A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS

Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing

Receiver Offset Cancellation in 90-nm PLD Integrated SERDES

Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver

A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR

A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links

Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System

A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector

A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes

An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range

A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking

A 14-b 30MS/s $0.75mm^{2}$ Pipelined ADC with On-Chip Digital Self-Calibration

A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration

Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique

A 1V 10b 30MSPS Switched-RC Pipelined ADC

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR

A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS

A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS

A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems

Low-jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA Applications

Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization

A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance

A 2.5Gb/s Burst-Mode CDR based on a $1/8^{th}$ rate Dual Pulse Ring Oscillator

Digitally-Enhanced Phase-Locking Circuits

A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface

A low noise buck converter with a fully integrated continuous time ΣΔ modulated feedback controller

A compact pulse-based charge pump in 0.13 μm CMOS

An Efficiency-Enhanced Integrated CMOS Rectifier with Comparator-Controlled Switches for Transcutaneous Powered Implants

Integrated Regulation for Energy-Efficient Digital Circuits

An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control

A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems

CMOS-Based MEMS Mirror Driver for Maskless Lithography Systems

Reliability Trends with Advanced CMOS Scaling and The Implications for Design

Evolution of CMOS Technology at 32 nm and Beyond

High-K/Metal Gate Technology: A New Horizon

Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems

Reverse Engineering in the Semiconductor Industry

Cochlear Implant Signal Processing ICs

An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory

A cost-effective digital front-end realization for 20-bit ΣΔ DAC in 0.13 μm CMOS

A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication

A High-Throughput Maximum a posteriori Probability Detector

A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS

A heterodyne phase locked loop with GHz acquisition range for coherent locking of semiconductor lasers in 0.13 μm CMOS

A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers

Towards a sub-2.5V, 100-Gb/s Serial Transceiver

Future Microprocessor Interfaces: Analysis, Design and Optimization

Time-Variant Characterization and Compensation of Wideband Circuits

High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications

PSP-Based Scalable MOS Varactor Model

An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs

Synthesis of Optimal On-Chip Baluns

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

Mismatch Characterization of Ring Oscillators

The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design

A 3.5mW 900MHz Down-converter with Multiband Feedback and Device Transconductance Reuse

A Highly Linear Broadband Variable Gain LNA for TV Applications

A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers

A 65 μW, 1.9 GHz RF to digital baseband wakeup receiver for wireless sensor nodes

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

A 1.7-GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAE

A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry

Comparative Studies of Common Control Schemes for Reference Tracking and Application of End-point Prediction

An Ultra-Low-Power Power Management IC for Wireless Sensor Nodes

A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity

A 610-MHz FIR Filter Using Rotary Clock Technique

A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems

A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches

Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design

Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory

A 37 ppm/°C Temperature Compensated CMOS ASIC with ±16 V Supply Protection for Capacitive Microaccelerometers

A 500MHz Low Phase-Noise A1N-on-Silicon Reference Oscillator

1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling Array Processor

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts

Obtaining Frequency Sensitivities to Variations Analytically from Parameterized Nonlinear Oscillator Phase Macromodels

Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices

Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization

FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area

A Comprehensive Phase-Transfer Model for Delay-Locked Loops

Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic Balance

Low-Voltage Multi-Mode Gm-C Channel Selection Filter for Mobile Applications

Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers

CMOS Low Noise Amplifier with Capacitive Feedback Matching

A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter

A 3.1-8.0 GHz MB-OFDM UWB transceiver in 0.18μm CMOS

A -90 dBm sensitivity 0.13 μm CMOS bluetooth transceiver operating in wide temperature range

On IIP2 Improvement by Injecting DC Offset at the Mixer in a Wireless Receiver

ECO chip: Energy Consumption Zeroize Chip with a 953MHz High-Sensitivity Radio Wave Detector for Standby Mode Applications

Understanding the Transient Behavior of Injection Locked LC Oscillators

A Wideband CMOS Linear Digital Phase Rotator

Low-Power CMOS Energy Detection Transceiver for UWB Impulse Radio System

An 80 MHz noise optimized continuous-time bandpass filter in 0.25 μm BiCMOS

A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS

A Q-enhanced Transformer Coupling Dynamic Dual-Mode 5GHz Bandpass NB / Interference Rejection UWB Filter

A Process and Temperature Compensated Two-Stage Ring Oscillator

Signal Processing Architectures for Low-Noise High-Resolution CMOS Image Sensors

A 1.8 $mm^{2},$ 11 mA, 23.2 dB-NF, discrete-time filter for GSM/WCDMA/WLAN using retiming technique

An Equalized Ultra-Wideband Channel-Select Filter with a Discrete-Time Charge-Domain Band-Pass IIR Filter

Cell Broadband Engine Processor Design Methodology

Implementation of the 65nm Cell Broadband Engine

Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection

A 2GHz, 7W (max) 64b $Power^{TM}$ Microprocessor Core

Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology

Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd

ASIC Design and Verification in an FPGA Environment

mm-Wave Silicon ICs: Challenges and Opportunities

65-nm CMOS, W-Band Receivers for Imaging Applications

A 4-channel 24-27 GHz UWB phased array transmitter in 0.13 μm CMOS for vehicular radar

A CMOS 22-29GHz Receiver Front-End for UWB Automotive Pulse-Radars

An X- and Ku-Band 8-Element Linear Phased Array Receiver

A 30-40 GHz 1:16 Internally Matched SiGe Active Power Divider for Phased Array Transmitters

A 60 GHz Power Amplifier in 90nm CMOS Technology

At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?

Process/Product Interactions in a Concurrent Design Environment

Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect

An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM

A 180 Kbit Embeddable MRAM Memory Module

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

Advanced Design Techniques for Integrated Voltage Controlled LC Oscillators

A 0.5-V 16 GHz-20 GHz differential injection-locked divider in 0.18-μm CMOS process

A 1V 4 GHz-and-10 GHz transformer-based dual-band quadrature VCO in 0.18 μm CMOS

A CMOS Image Sensor for DNA Microarrays

Active CMOS Array for Electrochemical Sensing of Biomolecules

A CMOS Array Sensor for Sub-800-ps Time-Resolved Fluorescence Detection

A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Integration of CMOS and MEMS Technologies in the Development of a Neural Imaging and Interface Device: Showcase of an Emerging Bioimaging Technique

Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots

Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation

Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates

Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications

Accurate Modeling of RF Circuit Blocks: Weakly-Nonlinear Narrowband LNAs

Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration

IEEE Custom Integrated Circuits Conference 2006

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

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Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

Proceedings of CICC 97 - Custom Integrated Circuits Conference

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A High-Throughput Maximum a posteriori Probability Detector

Content Provider	IEEE Xplore Digital Library
Author	Ratnayake, R. Kavcic, A. Gu-Yeon Wei
Copyright Year	2007
Description	Author affiliation: Harvard Univ., Cambridge (Ratnayake, R.)
Abstract	This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo decoding, can approach performance close to the channel capacity limit. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 MHz while consuming 2.4 W. The detector is implemented in a 0.13mum CMOS technology and has a die area of 9.9 $mm^{2}.$
Starting Page	455
Ending Page	458
File Size	388503
Page Count	4
File Format	PDF
ISBN	9781424407866
DOI	10.1109/CICC.2007.4405772
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Throughput Viterbi algorithm Bit error rate Delay Iterative algorithms Latches Circuits Decoding CMOS technology
Content Type	Text
Resource Type	Article

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