NDLI: A 54 MHz chip set for HDTV filtering

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2015 IEEE Custom Integrated Circuits Conference (CICC)

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

2011 IEEE Custom Integrated Circuits Conference (CICC)

IEEE Custom Integrated Circuits Conference 2010

2009 IEEE Custom Integrated Circuits Conference

2008 IEEE Custom Integrated Circuits Conference

2007 IEEE Custom Integrated Circuits Conference

IEEE Custom Integrated Circuits Conference 2006

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

Proceedings of CICC 97 - Custom Integrated Circuits Conference

Proceedings of Custom Integrated Circuits Conference

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

1992 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

IEEE Proceedings of the Custom Integrated Circuits Conference

High performance CMOS array with an embedded test structure

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea-of-gates

A 150 K gate 250 ps BiCMOS SOG with an emitter-follower CMOS (ECMOS) cell

A 30000 gate ECL gate array using advanced single poly technology and four level metal interconnect

A 20 K GaAs array with 10 K of embedded SRAM

A 150 K-circuit ASIC family using a DRAM technology

A new approach to event-driven analog/digital simulation

IDSIM2: an environment for mixed-mode simulation

ROOMMS-a relaxation-based, object-oriented, mixed-mode simulator

Development of an analog hardware description language

Behavioral analog circuit models for multiple simulation environments

A behavioral model of A/D converters using a mixed-mode simulator

Fast successive-approximation A/D converters

A self-calibrating 16 bit 6 mu s CMOS audio ADC

A first-order current-steering sigma-delta modulator

An 8-b 50-MHz 225-mW submicron CMOS ADC using saturation eliminated comparators

A 7-channel level generator chip for a VLSI digital tester

A high speed EEPROM configurable digital to analog convertor array

Low-cost CMOS algorithmic digital-analogue convertor for high-frequency applications

Integrated sensor and rangefinding analog signal processor

An active thin-film magnetic head with 60 MHz bandwidth and internal amplification of 58 dB

Design of a 64*64 photo current multiplexer for use in astronomical applications

A digital signal processor for linear sensors

Time integrating correlator (TIC) for real-time processing of spread-spectrum signals

ALPHA, a new contact type linear image sensor

Design considerations for CMOS switched-current filters

A 1.4 V switched capacitor filter

A high frequency fully differential BiCMOS operational amplifier

A high-speed CMOS amplifier with dynamic frequency compensation

Rapid yield estimation as a computer aid for analog cell design

An intelligent analog IC design system based on manipulation of design equations

Pole-zero simulator with component sensitivity analysis function

An accurate and compact model for the transient simulation of continuous-time filters

Logic simulation using a message-driven approach on MIMD computers

Mixed behavior-logic simulation in a hardware accelerator

iDEAS: a delay estimator and transistor sizing tool for CMOS circuits

A new circuit recognition and reduction method for pattern based circuit simulation

CHARMS: characterization and modeling system for accurate delay prediction of ASIC designs

Efficient on-chip delay estimation for leaky models of multiple-source nets

VLSI design theory: tenacious myths and economic constraints

Fundamentals on design management systems development

A mixed level simulator mega-FAL with novel data structure oriented to HDL statements

A 300 K-circuit ASIC logic family CAD system

A technical strategy for mixed analog-digital customs

A knowledge based simulation environment

Towards computer aided specification of analog components

High density central I/O circuits for CMOS

Crosstalk analysis of high-speed interconnects and packages

Effect of device and interconnect scaling on the performance and noise of packaged CMOS devices

A full 1.2 mu m CMOS ECL-CMOS-ECL converter with subnanosecond settling times

CMOS amplifiers incorporating a novel slew rate enhancement technique

Current control buffer for multi switching CMOS SOG

ISDN U transceiver analog front-end

Integration of a CMOS mixed-analog-digital eight channel speech transmission circuit

A CMOS analog front-end processor for an FDM system

A low-power low-noise CMOS compatible 80 V subscriber line interface circuit

A BiCMOS analog/digital array for cellular radio applications

A sigma-delta based square-law compandor

A programmable 32 tap digital interpolation filter in 1.5 mu m CMOS with 80 MHz output data rate

A 40 MHz programmable and reconfigurable filter processor

A VLSI grammar processing subsystem for a real time large vocabulary continuous speech recognition system

A complete audio decoder IC for US television stereo using serial arithmetic

A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compiler

A 25 MHz Viterbi FEC codec

An opto-electronic Viterbi traceback processor for decoding convolutional codes

Timing optimizations in a high-level synthesis system

Topology decomposition for area-minimum multi-stage complex gates synthesis

Real area-power-delay trade-off in EUCLID logic synthesis system

SAM: a data path allocation system

New design approach for configurable data-path

FIRGEN: a CAD system for automatic layout generation of high-performance FIR filter

Automatic synthesis of analog and sampled-data circuits in CMOS technology

Rule based CAD tools for analog circuit synthesis and layout compilation

MxSICO: a mixed analog digital compiler: application to oversampled A/D converters

An integrated PLL clock generator for 275 MHz graphic displays

A 18 Mb/s BiCMOS disk drive data separator

A CMOS VLSI chess microprocessor

A chip for realtime skeleting of images

A 66 MHz DSP-augmented RAMDAC for smooth-shaded graphic applications

A dynamically tracking clock distribution chip with skew control

A hybridised, multi-channel, charged-particle detecting and counting array

SYMCELL-a symbolic standard cell design system

High speed 0.55 micron BiCMOS family of ASICs

Building-cell design methodology for high-speed GaAs standard-cell LSIs

Clock skew reduction approach for standard cell

A flexible multi-port RAM compiler for datapath

A high performance one micron CMOS technology chip

An ADVANCELL 1.0 mainframe chipset-2.2 million transistors on 11 ICs

The WASP 2 WSI massively parallel processor demonstrators

Two-level pipelined systolic array graphics engine

SVP: serial video processor

A high performance SIMD processor for binary image processing

A flexible motion-vector estimation chip for real-time video codecs

IRIS: a 20 MHz Image Recognition Integrated System

A chip-set for lossless image compression

A real-time multi-kernel picture convolver

A laser direct write double-level-metal technology for rapid fabrication

AlInAs/GaInAs HBT IC technology

BEST: a BiCMOS-compatible super-self aligned ECL technology

A complementary selective epitaxial growth (CSEG) process and its application to high speed bipolar transistors

Precise capacitor structure suitable for submicron mixed analog/digital ASICs

A 0.8 mu m advanced single poly BiCMOS technology for high density and high performance applications

Turn-on transient imposed extrinsic base consideration in BiNMOS transistors

Comparative performance limits of MOSFET, MESFET and MODFET digital circuits

An integrated ASIC diagnosis system

Automotive electronics IC reliability

VLSI circuit design with built-in reliability using simulation techniques

An integrated system for circuit level hot-carrier evaluation

Novel fault-tolerant circuits for configurable mass memories

Memory system reliability improvement through associative cache redundancy

Estimation of power dissipation in CMOS combinational circuits

A reconfigurable content addressable memory

A sub-10 ns cache SRAM for high performance 32 bit microprocessors

A 6-ns 256-kbit BiCMOS TTL SRAM

Design of VLSI switch for highly parallel multiprocessor system

A 100 MHz floating point/integer processor

Yet another multiplier architecture

A 2.5 ns ECL 16*16 multiplier

3.5 K gate 32-bit ALU using GaAs HFET technology

A 20 MHz QAM chip with numerical controlled carrier generator for research in HDTV

A video rate rerastering IC

A 54 MHz chip set for HDTV filtering

A 500-MHz monolithic CRT video driver using a linear array

A VLSI DPCM encoder/decoder chip set for extended quality digital TV

A general purpose high speed equalizer

Fully-integrated correlated tuning processor for continuous-time filters

Implementation of a neuron dedicated to Kohonen maps with learning capabilities

A novel switched capacitor bidirectional associative memory

A neural network integrated circuit supporting programmable exponent and mantissa

A dynamic CMOS multiplier for analog neural network cells

A preprogrammed artificial neural network architecture in signal processing

A compact and general-purpose neural chip with electrically programmable synapses

Random address 32*32 programmable analog vector-matrix multiplier for artificial neural networks

An efficient relative placement algorithm for custom chip design

Direct solution of performance constraints during placement

A maze routing method of combined unity and infinity expansion distances

Multilayer area routing algorithm as an optimization problem

The effect of switch box flexibility on routability of field programmable gate arrays

New algorithms for placement and routing of custom analog cells in ACACIA

A new routing method for full custom analog ICs

A toolbox for ASIC testability automation

Testing embedded RAMs in ASIC chips

A structured approach to macrocell testing using built-in self-test

PEST-a tool for implementing pseudo-exhaustive self test

A universal test sequence for CMOS scan registers

Defect analysis and test generation for gate oxide shorts in CMOS ICs

A test strategy for a bit-serial VLSI chip with analog I/O

Boolean minimization using new ATPG techniques and saved test patterns

Exploring the design space in high-level synthesis

Design Assistant: an expert tool for ASIC design

Circuit partitioning and resynthesis

Automating the design of asynchronous sequential logic circuits

Logic synthesis of asynchronous circuits

An interactive graphical approach to module generator development

STAT: a schematic to artwork translator for custom analog cells

Hierarchical symbolic design methodology for large-scale datapaths

An interactive/automatic floor planner for hierarchically designed cell based VLSIs

Transformation-based layout optimization

Automatic verification of library-based IC designs

Labyrinth: a homogeneous computational medium

Third-generation architecture boosts speed and density of field-programmable gate arrays

An efficient logic block interconnect architecture for user-reprogrammable gate array

The implementation of hardware subroutines on field programmable gate arrays

An FPGA family optimized for high densities and reduced routing delay

A 150 MHz CMOS EPLD with mu W standby power

A user configurable gate array using CMOS-EPROM technology

Proceedings of the IEEE 1990 Custom Integrated Circuits Conference (Cat. No.90CH2860-5)

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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