NDLI: Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology

Content Provider	IEEE Xplore Digital Library
Author	Knickerbocker, J.U. Patel, C.S. Andry, P.S. Tsang, C.K. Paivikki Buchwalter, L. Sprogis, E. Hua Gan Horton, R.R. Polastre, R. Wright, S.L. Schuster, C. Baks, C. Doany, F. Rosner, J. Cordes, S.
Copyright Year	2005
Description	Author affiliation: IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA (Knickerbocker, J.U.; Patel, C.S.; Andry, P.S.; Tsang, C.K.; Paivikki Buchwalter, L.)
Abstract	System-on-chip (SOC) and system-on-package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two and three dimensional silicon integration technologies are emerging which likely support next generation high-volume electronic applications and may serve high-performance computing applications. This paper discusses a few emerging technologies which offer opportunities for circuit integration on-chip as well as on-package using fine pitch interconnection, silicon wafer processing and silicon carrier packaging technology. Advanced silicon carrier package technology with fine pitch (50/spl mu/m) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16/spl times/ increase over standard chip I/O, a 20/spl times/ to 100/spl times/ increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers and mini-multi-chip modules (MMCM) which integrate heterogeneous dies forming a single "virtual chip".
Starting Page	659
Ending Page	662
File Size	315517
Page Count	4
File Format	PDF
ISBN	0780390237
DOI	10.1109/CICC.2005.1568756
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon CMOS technology Integrated circuit interconnections Electronics packaging Integrated circuit technology System-on-a-chip Computer applications Wiring Ceramics Testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in