NDLI: The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

Content Provider	IEEE Xplore Digital Library
Author	Pham, D. Behnen, E. Bolliger, M. Hofstee, H.P. Johns, C. Kahle, J. Kameyama, A. Keaty, J. Le, B. Masubuchi, Y. Posluszny, S. Riley, M. Suzuoki, M. Wang, M. Warnock, J. Weitzel, S. Wendel, D. Yazawa, K.
Copyright Year	2005
Description	Author affiliation: IBM Syst. & Technol. Group, Austin, TX, USA (Pham, D.; Behnen, E.; Bolliger, M.; Hofstee, H.P.; Johns, C.; Kahle, J.)
Abstract	This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above challenges. A CELL processor consists of a 64 bit power architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multicore SoC, implemented in 90nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.
Starting Page	45
Ending Page	49
File Size	342910
Page Count	5
File Format	PDF
ISBN	0780390237
DOI	10.1109/CICC.2005.1568604
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design methodology Frequency Linux Clocks Thermal management Operating systems Real time systems Hardware Power system protection Content management
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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