NDLI: A digital DFT technique for verifying the static performance of A/D converters

Content Provider	IEEE Xplore Digital Library
Author	Choi, W. Vinnakota, B. Harjani, R.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA (Choi, W.; Vinnakota, B.; Harjani, R.)
Abstract	We present a reconfiguration DFT methodology for evaluating the static performance of a charge redistribution analog-to-digital converter. During the test mode, we reconfigure the ADC to operate as a capacitor ratio converter and measure the primary capacitor ratios which determine the transition voltages. Based on these estimated transition voltages, the static performance of the converter under test can be derived. To validate the methodology, we designed and fabricated an 11-bit charge redistribution ADC with the reconfiguration DFT technique in a 1.2 /spl mu/m CMOS process. The technique was used to reconstruct the integral (INL) and differential non-linearity (DNL) errors using a digital only tester. The INL and DNL results were verified with analog/digital bench equipment.
Sponsorship	IEEE Solid-State Circuits Soc
Starting Page	207
Ending Page	210
File Size	496102
Page Count	4
File Format	PDF
ISBN	0780384954
DOI	10.1109/CICC.2004.1358778
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Analog-digital conversion Design for testability Circuit testing Transfer functions CMOS process Switched capacitor circuits Switches Design methodology Application specific integrated circuits
Content Type	Text
Resource Type	Article

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