NDLI: A 36 MHz CMOS fixed-point G.728 low delay CELP integrated decoder-encoder

Content Provider	IEEE Xplore Digital Library
Author	Soon, W.B.H. Goyal, S. Liu Chong Hsu Yeo Lik Wee
Copyright Year	1996
Description	Author affiliation: Siemens Components Pte Ltd., Singapore (Soon, W.B.H.; Goyal, S.; Liu Chong Hsu; Yeo Lik Wee)
Abstract	The highly integrated JADE (Joint Audio Decoder-Encoder) device implements audio compression using either G.711, G.722 or G.728 compression algorithms. The integration of peripherals, interfaces and memories with a fixed point DSP (digital signal processor) to implement complex speech algorithms such as G.728, opens up the market for low cost digital telecommunications applications. Using the G.728 Low Delay Code Excited Linear Prediction (LD-CELP) algorithm, the device compresses/decompresses a digitized PCM (64 kbps) or linear (128 kbps) voice signal to/from a 16 kbps bit stream. The device has been fabricated in a 0.5 /spl mu/m n-well CMOS process.
Starting Page	367
Ending Page	370
File Size	508402
Page Count	4
File Format	PDF
ISBN	0780331176
DOI	10.1109/CICC.1996.510577
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-05-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing algorithms Decoding Audio compression Compression algorithms Digital signal processing Digital signal processors Speech processing Costs Delay lines Prediction algorithms
Content Type	Text
Resource Type	Article

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A 36 MHz CMOS fixed-point G.728 low delay CELP integrated decoder-encoder