NDLI: A 622 Mbps ATM physical layer ASIC and its "design for test" methods

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Proceedings IEEE Symposium on Computers and Communications

A 622 Mbps ATM physical layer ASIC and its "design for test" methods

Content Provider	IEEE Xplore Digital Library
Author	Chan Kim Yeong Ho Park Doo Sub Eom Jae Keun Kim
Copyright Year	1997
Abstract	A 622 Mbps ATM physical layer ASIC design is described. This ASIC performs the full 622 Mbps ATM physical layer functions according to the ITU-T I.432 and ATM Forum UNI standards. The cells are processed at 77.76 MHz speed but most of the other STM related circuits run at te 19.44 MHz clock rate. Each functional block is explained with its robust synchronization mechanism among other processing blocks. The design aspects and techniques for the ASIC test are explained for scan test and additional functional test in a reduced frame mode which was specially designed for this ASIC. Most of the basic functions were verified through loop-back test including fiber loops.
Starting Page	349
Ending Page	353
File Size	491424
Page Count	5
File Format	PDF
ISBN	0818678526
DOI	10.1109/ISCC.1997.616023
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-07-01
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Physical layer Application specific integrated circuits Design methodology Asynchronous transfer mode Clocks Containers Robustness Circuit testing Frequency synchronization Bandwidth
Content Type	Text
Resource Type	Article

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