NDLI: A new systolic array algorithm for memory-based VLSI array implementation of DCT

Content Provider	IEEE Xplore Digital Library
Author	Chiper, D.-F.
Copyright Year	1997
Description	Author affiliation: Dept. of Appl. Electron., Tech. Univ. Gh. Asachi, Iasi, Romania (Chiper, D.-F.)
Abstract	A new approach for a memory-based VLSI realization of the 1D discrete cosine transform (1D-DCT) that significantly improves the previous designs is presented. This approach is based on a new formulation of an odd prime-length DCT algorithm. It uses two half-length cyclic convolutions with the same form, which are such reformulated that multipliers can be efficiently replaced by small biport ROMs and computed in parallel. Using this approach, high structural regularity, low hardware cost of the PE's and average computation time, and low I/O cost can be obtained. So, the average computation time has been reduced to one half and the throughput has been doubled, when compared with that of Guo et al. (1992). Thus an efficient systolic array for DCT, which is well suited for VLSI realization, can be obtained. It possesses also a much lower control complexity, it simpler interconnection structure, and a simpler hardware structure of the PEs, having thus a shorter cycle time. Moreover, it owns all other outstanding features of the VLSI array proposed by Guo et al.
Starting Page	297
Ending Page	301
File Size	364496
Page Count	5
File Format	PDF
ISBN	0818678526
DOI	10.1109/ISCC.1997.616015
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-07-01
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Systolic arrays Very large scale integration Discrete cosine transforms Signal processing algorithms Hardware Costs Convolution Parallel processing Concurrent computing Algorithm design and analysis
Content Type	Text
Resource Type	Article

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