NDLI: A Framework for Fault Tolerant Real Time Systems Based on Reconfigurable FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Gericota, M.G. Lemos, L.F. Alves, G.R. Barbosa, M.M. Ferreira, J.M.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng., ISEP, Porto (Gericota, M.G.; Lemos, L.F.; Alves, G.R.)
Abstract	To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.
Starting Page	131
Ending Page	138
File Size	249284
Page Count	8
File Format	PDF
ISBN	0780397584
DOI	10.1109/ETFA.2006.355409
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-20
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerant systems Real time systems Field programmable gate arrays Reconfigurable logic Manufacturing Costs Fluctuations Electromagnetic fields Electromagnetic radiation Circuits
Content Type	Text
Resource Type	Article

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