NDLI: Minimum size primitives for efficient VLSI implementation of DDO-based ciphers

Content Provider	IEEE Xplore Digital Library
Author	Moldovyan, A.A. Moldovyan, N.A. Sklavos, N.
Copyright Year	2004
Description	Author affiliation: Specialized Center of Program Syst. "SPECTR", Kantemirovskaya, Russia (Moldovyan, A.A.; Moldovyan, N.A.)
Abstract	This work focuses the problem of increasing the performance of the ciphers based on data-dependent (DD) operations (DDO) for VLSI implementations. New minimum size primitives are proposed to design DDOs. Using advanced DDOs instead of DD permutations (DDP) in the DDP-based iterative ciphers Cobra-H64 and Cobra H128 the number of rounds has been significantly reduced yielding enhancement of the "performance per cost" value. To obtain further enhancement of this parameter a new crypto-scheme based on the advanced DDOs is proposed. The FPGA implementation of the proposed crypto-scheme achieves higher throughput value and minimizes the allocated resources than the conventional designs.
Sponsorship	Dallas Chapter/IEEE CAS IEEE Circuits and Syst. Soc
Starting Page	807
Ending Page	810
File Size	432543
Page Count	4
File Format	PDF
ISBN	0780382714
DOI	10.1109/MELCON.2004.1347054
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-12
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Cryptography Field programmable gate arrays Communication system security Information security Hardware Data security Data engineering Throughput Resource management
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Area optimized architecture and VLSI implementation of RC5 encryption algorithm

An ultra high speed architecture for VLSI implementation of hash functions

VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher

On the FPGA Implementation of HAVAL Hash Function

Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system

Efficient VLSI implementation of modern symmetric block ciphers

VLSI implementation of the advanced encryption standard system with error detection

High-speed hardware implementations of the KASUMI block cipher

VLSI Implementation of High-Speed Cellular Automata Encryption Algorithm

Minimum size primitives for efficient VLSI implementation of DDO-based ciphers

Similar Documents

Area optimized architecture and VLSI implementation of RC5 encryption algorithm

An ultra high speed architecture for VLSI implementation of hash functions

VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher

On the FPGA Implementation of HAVAL Hash Function

Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system

Efficient VLSI implementation of modern symmetric block ciphers

VLSI implementation of the advanced encryption standard system with error detection

High-speed hardware implementations of the KASUMI block cipher

VLSI Implementation of High-Speed Cellular Automata Encryption Algorithm

Minimum size primitives for efficient VLSI implementation of DDO-based ciphers