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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gerfers, F. Ortmanns, M. Schmitz, P. Manoli, Y. Soh, K.M. |
| Copyright Year | 2003 |
| Description | Author affiliation: Inst. of Microsystem Technol., Albert-Ludwigs-Univ., Freiburg, Germany (Gerfers, F.; Ortmanns, M.; Schmitz, P.; Manoli, Y.) |
| Abstract | The design of a clock-jitter insensitive multibit digital-to-analog converter (DAC) topology for high-performance low-power continuous-time /spl Sigma//spl Delta/ modulators is presented. The 9 level DAC circuit uses a time-variant feedback pulse shape to reduce both the clock jitter influence as well as the slew rate and bandwidth requirements of the used amplifiers and therewith the overall power consumption of the modulator. Additional it will be shown that the proposed concept is suitable for very low supply voltages. The DAC architecture was exemplary implemented in a second-order 2MHz CT /spl Sigma//spl Delta/ modulator for UMTS applications operating at a sample frequency of 50MHz. The modulator operates from a single 1.8V power supply and achieves a 11-bit dynamic range for the 2MHz passband. |
| Sponsorship | IEEE IEEE Circuits and Syst. Soc. Univ. of Sharjah Etisalat College of Eng. Emirates Telecommunications Corp |
| Starting Page | 958 |
| Ending Page | 961 |
| File Size | 276730 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780381637 |
| DOI | 10.1109/ICECS.2003.1301667 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-12-14 |
| Publisher Place | United Arab Emirates |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Clocks Jitter Pulse amplifiers Pulse modulation Digital-analog conversion Circuit topology Digital modulation Feedback circuits Pulse circuits Pulse shaping methods |
| Content Type | Text |
| Resource Type | Article |
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