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Content Provider | IEEE Xplore Digital Library |
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Author | Grossschadl, J. Kamendje, G.-A. |
Copyright Year | 2003 |
Description | Author affiliation: Inst. for Appl. Inf. Process. & Commun., Graz Univ. of Technol., Austria (Grossschadl, J.; Kamendje, G.-A.) |
Abstract | This paper presents the design and implementation of a single-cycle multiply/accumulate (MAC) unit for 32-bit RISC cores. Our design facilitates not only the processing of common DSP routines but also arithmetic with very long integers. The proposed MAC unit can perform a variety of operations including (32/spl times/32)-bit signed/unsigned multiplication, (32/spl times/32+64)-bit signed/unsigned multiplication-accumulation, and (32/spl times/32+32+32)-bit multiplication-accumulation on unsigned integers. The latter one is the core operation of multiple-precision multiplication and hence very useful for public-key cryptography. We introduce a radix-4 Booth multiplier that implements the mentioned functionality with a minimum number of full adder cells arranged in an optimized array structure. Our experimental implementations based on a 0.6 /spl mu/m standard cell library show that the MAC unit consists of roughly 8,000 gates and has a delay of less than 25 ns. |
Sponsorship | IEEE IEEE Circuits and Syst. Soc. Univ. of Sharjah Etisalat College of Eng. Emirates Telecommunications Corp |
Starting Page | 739 |
Ending Page | 742 |
File Size | 332822 |
Page Count | 4 |
File Format | |
ISBN | 0780381637 |
DOI | 10.1109/ICECS.2003.1301891 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2003-12-14 |
Publisher Place | United Arab Emirates |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Digital signal processing Public key cryptography Registers Arithmetic Computer architecture Microprocessors Signal design Adders Software libraries Delay |
Content Type | Text |
Resource Type | Article |
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