NDLI: A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

Content Provider	IEEE Xplore Digital Library
Author	Chua-Chin Wang Hsien-Chih She Hu, R.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan (Chua-Chin Wang; Hsien-Chih She)
Abstract	A CMOS local oscillator using a programmable DLL (delay lock loop)-based frequency multiplier to synthesize carrier frequencies from 1.1 GHz to 1.5 GHz is presented. The frequency of the output clock is 7/spl times/ to 10/spl times/ of an input reference clock. No LC-tank is used in the proposed design, such that the power dissipation as well as the active area are drastically reduced. The design is carried out using the TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the VCDTL (voltage-controlled delay tap line) at the mid point of the working range. Meanwhile, the power dissipation of the physical chip measures only 52.2 mW at 1.2 GHz output.
Sponsorship	IEEE CAS Soc. IEEE Region 8
Starting Page	69
Ending Page	72
File Size	246966
Page Count	4
File Format	PDF
ISBN	0780375963
DOI	10.1109/ICECS.2002.1045335
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-15
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers Clocks Power dissipation Voltage Local oscillators Tracking loops Frequency locked loops CMOS process Power supplies Delay effects
Content Type	Text
Resource Type	Article

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