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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Palumbo, G. Pappalardo, D. Gaibotti, M. |
| Copyright Year | 2002 |
| Description | Author affiliation: Dipt. Elettrico Elettronico e Sistemistico, Catania Univ., Italy (Palumbo, G.) |
| Abstract | In this paper, both a charge pump which changes its number of stages to achieve the minimum power consumption and a regulated voltage reference based on it is presented. The charge pump can modifies the number of stages from 1 to 3 through a proper assigning of the clock phases, and it uses the same amount of capacitance (i.e., silicon area) in all the topologies. The voltage regulator, based on the adaptive charge pump can dynamically select the equivalent stage behavior to maximize the power efficiency under power supply changes. The behavior of the circuits were confirmed through Eldo simulation using a 0.35 /spl mu/m CMOS EEPROM technology. |
| Sponsorship | IEEE CAS Soc. IEEE Region 8 |
| Starting Page | 61 |
| Ending Page | 64 |
| File Size | 224353 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780375963 |
| DOI | 10.1109/ICECS.2002.1045333 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-09-15 |
| Publisher Place | Croatia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Voltage Regulators Charge pumps CMOS technology Energy consumption Clocks Capacitance Silicon Circuit topology Power supplies |
| Content Type | Text |
| Resource Type | Article |
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