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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | De Caro, D. Mazzocca, N. Napoli, E. Saggese, G.P. Strollo, A.G.M. |
| Copyright Year | 2001 |
| Description | Author affiliation: Dept. of Electron. & Telecommun. Eng., Naples Univ., Italy (De Caro, D.) |
| Abstract | A novel test pattern generator for the built-in self-test technique in testable combinational circuits is proposed. The presented solution is based on a hybrid testing reconfigurable test pattern generator, that uses a shift register reacted through two different networks: it firstly reproduces a pseudo-random sequence of test patterns using a linear feedback combinational network and then reproduces deterministic precalculated test patterns, useful to detect hard faults, using a nonlinear feedback combinational network. For the proposed approach, a synthesis tool (based on state space heuristic search and the "selfish gene" genetic algorithm) able to determine test pattern generator for a given test set, is also proposed. Experiments to evaluate synthesis time and the test sequence length are conducted on well-known ISCAS'85 circuits. Comparison with previous techniques shows the effectiveness of proposed solution. |
| Sponsorship | IEEE CAS Soc. Univ. Malta |
| Starting Page | 745 |
| Ending Page | 748 |
| File Size | 444903 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780370570 |
| DOI | 10.1109/ICECS.2001.957582 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-09-02 |
| Publisher Place | Malta |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit testing Test pattern generators Combinational circuits Automatic testing Feedback Circuit synthesis Network synthesis Built-in self-test Shift registers Electrical fault detection |
| Content Type | Text |
| Resource Type | Article |
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