NDLI: A parallel 3D DCT architecture for the compression of integral 3D images

Content Provider	IEEE Xplore Digital Library
Author	Aggoun, A. Jalloh, I.
Copyright Year	2001
Description	Author affiliation: 3D Imaging Technol. Group, De Montfort Univ., Leicester, UK (Aggoun, A.)
Abstract	A new VLSI architecture for the computation of the three-dimensional discrete cosine transform (3D DCT) for compression of integral 3D images is proposed. The 3D DCT is decomposed into 1D DCTs computed in each of the three dimensions. The architecture is a parallel structure which computes an N/spl times/N/spl times/N-point DCT by computing N N/spl times/N 2D DCTs in parallel and feeding each of the computed 2D DCT coefficients into a final ID DCT block. The architecture uses 5N/sup 2//2 multiplier-accumulators to evaluate N/spl times/N/spl times/N-point DCT's at a rate of N complete 3D DCT coefficients per clock cycles, where N is even. The architecture is regular and modular and as such it is suitable for VLSI implementation. The proposed architecture has a better area-time performance than previously reported 3D DCT architectures. Also, the proposed architecture reduces the initial delay by a factor of N.
Sponsorship	IEEE CAS Soc. Univ. Malta
Starting Page	229
Ending Page	232
File Size	364519
Page Count	4
File Format	PDF
ISBN	0780370570
DOI	10.1109/ICECS.2001.957722
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-02
Publisher Place	Malta
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Image coding Computer architecture Lenses Microoptics Very large scale integration Concurrent computing Optical imaging Assembly Delay
Content Type	Text
Resource Type	Article

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