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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hiasat, A.A. |
| Copyright Year | 1996 |
| Description | Author affiliation: Dept. of Electron. Eng., Princess Sumaya Univ. Coll. for Technol., Amman, Jordan (Hiasat, A.A.) |
| Abstract | Design of Residue Number system Multipliers has received considerable attention in the last few years. This paper presents a new approach for designing modular multipliers using combinational logic technique. The idea is based on constructing a truth table whose inputs are the bits of the multiplicand and the multiplier. The outputs are the bits of the modular product realizing any minimized boolean function is achieved using two levels of gates. A VLSI implementation of module 5 has been accomplished. Compared to most recent developed approach, our new technique requires less integrated circuit area and operates at a higher speed. |
| Starting Page | 935 |
| Ending Page | 938 |
| File Size | 293642 |
| Page Count | 4 |
| File Format | |
| ISBN | 078033650X |
| DOI | 10.1109/ICECS.1996.584539 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-10-16 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Logic design Arithmetic Minimization methods Educational institutions High speed integrated circuits Concurrent computing Fast Fourier transforms Discrete Fourier transforms Digital filters |
| Content Type | Text |
| Resource Type | Article |
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