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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Seidel, D. Raju, A. Bayoumi, M.A. |
| Copyright Year | 1996 |
| Description | Author affiliation: Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA (Seidel, D.) |
| Abstract | In this paper, a scalable shared buffer switch architecture for asynchronous transfer mode (ATM) is proposed. It has O(/spl radic/N) complexity for the memory bandwidth requirement and the maximum crosspoint switch size, together with O(N) scalability for buffer memory size. In this architecture, multiple buffer memories are used between the input and output side crosspoint switches. By eliminating the use of input and output time division multiplexing, the new switch architecture is an improvement over the standard shared buffer approach. The proposed switch architecture is able to keep the crosspoint switches from growing as O(N/sup 2/) as is the case in the pure multibuffer architecture. It offers a good compromise between the standard shared buffer and shared multibuffer architectures. Architectural and implementation details are discussed and a quantitative comparison between the buffer architectures is given. Implementation of an 8/spl times/8 switch in 1.0 /spl mu/m CMOS technology is described. |
| Starting Page | 772 |
| Ending Page | 775 |
| File Size | 389190 |
| Page Count | 4 |
| File Format | |
| ISBN | 078033650X |
| DOI | 10.1109/ICECS.1996.584476 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-10-16 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Switches Asynchronous transfer mode Random access memory Bandwidth Switching converters CMOS technology Read-write memory Computer architecture Memory architecture Time division multiplexing |
| Content Type | Text |
| Resource Type | Article |
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