NDLI: Novel wafer level package technology studies for image sensor devices

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2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)

2011 IEEE 13th Electronics Packaging Technology Conference

2010 12th Electronics Packaging Technology Conference

2009 11th Electronics Packaging Technology Conference

2008 10th Electronics Packaging Technology Conference

2007 9th Electronics Packaging Technology Conference

2006 8th Electronics Packaging Technology Conference

2005 7th Electronic Packaging Technology Conference

Volume 2 - 2005

Volume 1 - 2005

Proceedings of 7th Electronics Packaging Technology Conference (IEEE Cat. No.05EX1233C)

Conference committee

Table of contents

Quilt packaging: a new paradigm for interchip communication

Through wafer copper via for silicon based SiP application

Industrially compatible PCB stacking technology for miniaturized sensor systems

An integrated and compact ISM bandpass filter using combline structures

Design and development of stacked die technology solutions for memory packages

Electrical design and specification challenges for high speed serial links

Impact of analog/digital ground design on circuit functionality and radiated EMI

10 Gbps backplane design methodology with sensitivity analysis and statistical analysis

Minimizing reflections and cross-talk in chip packages

Power integrity/signal integrity co-simulation for fast design closure

Influence of component position on lead-free solder interconnections during drop test

Drop impact life prediction model for wafer level chip scale packages

Drop impact life prediction models with solder joint failure modes and mechanisms

Prediction of board-level reliability of chip-scale packages under consecutive drops

Response spectra analysis for transient structural responses of board-level electronic packages subjected to half-sine impact acceleration pulses

Encapsulation and packaging of biosensor

Disposable bio-microfluidic package with passive fluidic control

Very thin packaging of capped MEMS accelerometer device

Study on the packaging technology for a high-G MEMS accelerometer

High density vertical probe card fabrication with low cost and high precision characteristics by using MEMS process

The analysis of the bending and twisting moments induced sweep deflection for semiconductor package applications

Effect of power cycling duration on coupled power and thermal cycling reliability of board-level chip-scale packages

Failure study of Sn-Ag-Cu lead-free solder joint by digital image speckle analysis (DISA)

Digital image correlation and its applications in electronics packaging

Electromigration effect on Cu-pillar(Sn) bumps

Wafer level processing on re-built wafer for chip stacking

A novel approach of depositing embedded resistors

Self assembly of microcomponents on patterned substrate using capillary force

Novel wafer level package technology studies for image sensor devices

Parametric design and solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Measurement of electrical parameters of silicon up to 60GHz

Crosstalk analysis in frequency and time domain using FDTD-VF method

High frequency characterization of 100 micron pitch wafer level package interconnects

Circuit model of elastomer probe for fine pitch wafer level package test applications

Development of demonstrator kit for designing practical EMC compliant system

Multi-level numerical analysis on the reliability of Cu/low-k interconnection in FCBGA package

Finite element analysis on the thermo-mechanical behavior of flip chip packages with Au stud bump and nonconductive paste

Predictive solder joint reliability assessment of board-on-chip package for DDR-II DRAM application

Compliance, deformation and thermal fatigue behavior of multi-copper-column interconnects

Numerical analysis by 3D finite element wire bond simulation on Cu/low-k structures

Temperature reduced direct bonding by plasma assisted wafer surface pre-treatment

Assessment of vacuum lifetime in nL-packages

Next generation low stress plastic cavity package for sensor applications

Through-wafer interconnection by deep damascene process for MEMS and 3D wafer level packaging

Wafer level thin film encapsulation for MEMS

Study of PCB strains and component position under board level drop test

Drop test reliability improvement of lead-free fine pitch BGA using different solder ball composition

Drop reliability performance assessment for PCB assemblies of chip scale packages (CSP)

Correlation between package-level ball impact test and board-level drop test

Investigating the cyclic bending of PCB subassembly during board level drop test

Bondability and reliability for insulated wirebonding process with 63/spl mu/m pitch capability

Assembly yield enhancement of electroless Ni-P UBM/Pb-free solder joints

Modeling energy transfer to copper wire for bonding in an inert environment

Implementation of advanced ball printing technology for high yield bumping of wafer chip scale packages

Evaluation of wirebond and flip-chip interconnects of a leadless plastic package for RF applications

LTCC based integration for RF applications

A compact and wideband rectangular dielectric resonator antenna

High frequency characteristics of low temperature processing and high density integrated capacitor on organic substrates

4-dimensional design analysis and optimization of system-in-package

Thermomechanical design for reliability of WLPs with compliant interconnects

Optimal design in enhancing board-level thermomechanical and drop reliability of package-on-package stacking assembly

Modeling the performance of flexible substrates for lead-free applications

Void of leaded and lead-free solder paste on different PCB surface pad finish under various reflow conditions - further investigation on void of SnInAgBi lead-free soldering paste

Development of no-flow underfill materials and processes for Pb-free flip chip applications

Nanoindentation on SnAgCu lead-free solder and analysis

Silver glues and lead-free alloys in die attach of power devices

40Gb/s parallel optical interconnection module for optical backplane application

Ultra small form factor plastic package transceiver modules for large core fiber systems

Design and evaluation of the 10-Gbps electrical transmission interface board for an optical backplane

Fundamental analysis of VCSEL emission for evaluation of optical coupling efficiency

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)

Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003)

4th Electronics Packaging Technology Conference, 2002.

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)

Proceedings of 2nd Electronics Packaging Technology Conference (Cat. No.98EX235)

Proceedings of the 1997 1st Electronic Packaging Technology Conference (Cat. No.97TH8307)

Novel wafer level package technology studies for image sensor devices

Content Provider	IEEE Xplore Digital Library
Author	Viswanadam, G. Bieck, F. Suthiwongsunthor, N.
Copyright Year	2005
Description	Author affiliation: Schott Adv. Packaging Singapore Pte Ltd. (Viswanadam, G.; Bieck, F.; Suthiwongsunthor, N.)
Abstract	Wafer level package for optical image sensor devices are known to be processed by re-routing of the bond pads to the back side of the chip, through (T) contacts located at the die edges. Bond pad back via contact wafer level packaging technology has been developed by Schott Electronic Packaging GmbH, Germany, which is proven to be with a number of advantages over the mechanically processed (T) contact wafer level packages. Direct contact of the bond pads from the back side of the chip offers much shorter transmission paths to the board assemblies, thus allowing faster signal speed, efficient thermal conduction and many added advantages. Also, the new technology offers area contacts with in the seal ring/isolation boundary of the device, there-by providing much higher performance for the packaged devices. The reliability of this new WLP technology has been demonstrated by testing the same for various reliability test conditions as per JEDEC/JIS standards. This paper discusses the process technology and reliability tests/results carried out on a consumer application chip, namely image sensor device
File Size	3660660
File Format	PDF
ISBN	0780395786
DOI	10.1109/EPTC.2005.1614385
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Image sensors Wafer bonding Isolation technology Testing Electronics packaging Optical devices Electronic packaging thermal management Optical sensors Assembly
Content Type	Text
Resource Type	Article

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