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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Steigerwald, J.M. |
| Copyright Year | 2008 |
| Description | Author affiliation: Intel Corp., Hillsboro, OR (Steigerwald, J.M.) |
| Abstract | Chemical mechanical polishing (CMP) has traditionally been considered an enabling technology. CMP was first used in the early 1990s for BEOL metallization to replanarize the wafer substrate thus enabling advanced lithography which was becoming ever more sensitive to wafer surface topography. Subsequent uses of CMP included density scaling via shallow trench isolation and interconnect formation via copper CMP. As silicon devices scale to 45 nm and beyond however, a large number of new uses of CMP are considered attractive options to enable new transistor technologies. These new uses will demand improved CMP performance (uniformity, topography, low defects) at lower cost which will in turn require breakthroughs in hardware, software, metrology and materials (slurry, pad, cleaning chemicals). This paper reviews the module level and integration challenges of applying traditional CMP steps to enable Hi-K metal gate for 45 nm technology and to advance Cu metallization from 65 nm to 45 nm node. These challenges are then considered with respect to new CMP applications considered for 32 nm and beyond. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1002345 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424423774 |
| ISSN | 81642284 |
| DOI | 10.1109/IEDM.2008.4796607 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-12-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Chemical technology Isolation technology Metallization Copper Lithography Surface topography Silicon devices Costs Hardware Software performance |
| Content Type | Text |
| Resource Type | Article |
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