NDLI: Feasibility of fault analysis based on intentional electromagnetic interference

Content Provider	IEEE Xplore Digital Library
Author	Takahashi, J. Hayashi, Y. Homma, N. Fuji, H. Aoki, T.
Copyright Year	2012
Description	Author affiliation: Tohoku University, 6-6-05, Aramaki Aza Aoba, Aoba-ku, Sendai-shi, 980-8579, Japan (Hayashi, Y.; Homma, N.; Aoki, T.) \|\| NTT Secure Platform Laboratories, Nippon Telegraph and Telephone Corporation, 3-9-11 Midori-cho, Musashino-shi, Tokyo 180-8585, Japan (Takahashi, J.; Fuji, H.)
Abstract	This paper presents the feasibility of fault analysis using intentional electromagnetic interference (IEMI). Fault analysis (FA) is a kind of implementation attack that intentionally extracts a secret key embedded in a secure device such as a smart card. An attacker injects a computational fault during the cryptographic calculation and he can extract a secret key. Recently, Hayashi et al. showed that temporal faults could be remotely injected during the cryptographic calculation using IEMI. They showed a case study in which an Advanced Standard Encryption (AES) secret key could be extracted through fault analysis. However, the characteristics of faults that can be induced by IEMI were not described. And, a threat of various FAs was not clear. In this paper, we examine in detail how the IEMI fault injection affects the fault occurrence of intermediate states in a cryptographic module and investigate the distribution of the IEMI generated faults. Furthermore, we classify previous FAs with respect to an attack model such as the type of faults needed to achieve a successful attack, and discuss the feasibility of FAs using IEMI based on the experimental results.
Starting Page	782
Ending Page	787
File Size	330442
Page Count	6
File Format	PDF
ISBN	9781467320610
ISSN	21581118
e-ISBN	9781467320603
DOI	10.1109/ISEMC.2012.6351665
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Encryption Doped fiber amplifiers Electromagnetic interference Laser beams
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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