NDLI: Spread spectrum clock generator with delay cell array to reduce the EMI from a high-speed digital system

Content Provider	IEEE Xplore Digital Library
Author	Jonghoon Kim Dong Gun Kam Joungho Kim
Copyright Year	2004
Description	Author affiliation: Memory Div., Samsung Electron., Kyeonggi-Do, South Korea (Jonghoon Kim)
Abstract	In high-speed digital systems, most of the EMI from the system is caused by high-speed digital clock drivers and synchronized circuits. In order to reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional spread spectrum clock generator with a phase locked loop (SSCG-PLL) has been implemented by controlling period jitter. However, the conventional SSCG-PLL becomes more difficult to implement at higher clock frequencies, in the GHz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome these problems associated with the random period jitter, we propose a spread spectrum clock generator with a delay cell array (SSCG-DCA), which controls the position of clock transitions. Measurement and simulation have demonstrated that the proposed SSCG-DCA is easier to implement and attenuating the EMI is more effective compared with the conventional SSCG-PLL. The proposed SSCG-DCA was implemented on a chip using a 0.35 /spl mu/m CMOS process and a 9 dB attenuation of the EMI was achieved at 390 MHz.
Starting Page	820
Ending Page	825
File Size	460306
Page Count	6
File Format	PDF
ISBN	0780384431
DOI	10.1109/ISEMC.2004.1349928
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Spread spectrum communication Clocks Delay Electromagnetic interference Digital systems Jitter Phase locked loops Frequency Attenuation Driver circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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