NDLI: A resonance-free power delivery system design methodology applying 3D optimized extended adaptive voltage positioning

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2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)

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2008 IEEE-EPEP Electrical Performance of Electronic Packaging

Power integrity I

Architecture constraints over dynamic current consumption

Verification and co-design of the package and die power delivery system using wavelets

3D power distribution network co-design for nanoscale stacked silicon ICs

Designs of signal-ground bump-patterns for minimizing the simultaneous switching noise in a ball grid array

High speed link

Design and analysis of a TB/sec memory system

Statistical link analysis of high-speed memory I/O interfaces during simultaneous switching events

Pseudo-differential signaling scheme based on 4b/6b multiwire code

On-chip bus signaling using passive compensation

An active crosstalk reduction technique for parallel high-speed links in low cost wirebond BGA packages

Signal integrity 1

SSN mitigation by means of a 2D EBG structure with square patches and meander lines

Compact expressions for period jitter of global binary clock trees

Multimode signaling on non-ideal channels

CMOS circuit simulation using Latency Insertion Method

Chip-package co-design methodology for global co-simulation of re-distribution layers (RDL)

On-chip oscilloscope for signal integrity characterization of interconnects in 130nm CMOS technology

Measurement techniques for on-chip power supply noise waveforms based on fluctuated sampling delays in inverter chain circuits

Correlation of PDN impedance with jitter and voltage margin for high speed channels

Accurate resistance, inductance, capacitance, and conductance (RLCG) from uniform transmission line measurements

Open forum (Posters) I

Design, modeling, and characterization of embedded electromagnetic band gap (EBG) structure

Simulation of worst case switching noise on a DDR2 interface

Placement of shorting vias for power integrity in multi-layered structures

Efficient analysis for multilayer power-ground planes with multiple vias and signal traces in an advanced electronic package

Analysis of entire power distribution system of chip, package and board for high speed IO design

Discussing impedance distribution with multiple stimulating sources in power distribution system design and simulation

A resonance-free power delivery system design methodology applying 3D optimized extended adaptive voltage positioning

Analysis of EBG structures using SPICE models of multiple planes

Multi-GHZ modeling and characterization of on-chip power delivery network

Accurate parasitic inductance determination of a ceramic capacitor through 2-port measurements

Correlation of On-Die capacitance for power delivery network

Hierarchical and adaptive finite-element reduction-recovery method for large-scale power and signal integrity analysis of high-speed IC and packaging structures

A novel stopband-enhanced EBG planes using an Embedded Slow-wave Structure in Low-cost RF-SiP

Ultra wideband wireless serial data communication at 10Gb/s in CMOS 90nm

Effective resolution of design issues in telecommunication blade systems

A dual-slope signaling scheme to suppress electromagnetic interference (EMI) with sustaining eye margin

Characterization of halogen-free package materials using cavity resonators

Development of a cost-reduced package thru DOE validation and zero-margin design concept

Forwarded clock based receiver characterization methodology for statistical full link analysis tools

Analysis of noise coupling from printed circuit board to shielding enclosure

Power integrity II

Effectiveness of on-die decoupling capacitance in improving chip performance

An adaptive on-chip ESR controller scheme in power distribution network for simultaneous switching noise reduction

2008 IEEE electrical performance of electronic packaging suppression of vertical coupling using Electromagnetic Band Gap structures

Including the impact of connecting vias in the performance metric evaluation for board-level optimization of decoupling capacitors

Robust iterative finite element solver for multi-terminal power distribution network resistance extraction

The design of continuous-time linear equalizers using model order reduction techniques

Parallel algorithm for analysis of high-speed interconnects

Nonlinear circuit solver with linear interconnect load

Compact macromodeling of electrically long interconnects

Passivity Enforcement via Quadratic Programming for element-by-element rational function approximation of passive network matrices

Signal integrity II

Sensitivity computation of interconnect capacitances with respect to geometric parameters

An analysis on measurement sensitivity of Short-Pulse Propagation technique using a virtual test bench

An efficient inductance extraction algorithm for 3-D interconnects with frequency dependent nonlinear magnetic materials

High frequency loss characterization of FCPBGA package materials with humidity and temperature variation

Open forum (posters) II

A Simple method of generating causal broadband RLGC models for CPW transmission lines with surface roughness

Fast iterative solution algorithms for the frequency-domain layered finite-element based analysis of large-scale on-chip interconnect structures

Compact on-chip wire models for the clock distribution of high-speed I/O interfaces

Parallel full-chip transient simulation at transistor level

Design-performance aspects of Glass Ceramic in comparison to Alumina Ceramic and organic FCPBGA packages for high link densities of high speed SerDes

Eliminating via-plane coupling using ground vias for high-speed signal transitions

Transient simulation of lossy interconnects using the Latency Insertion Method (LIM)

Effects of partially broken HF signal return on different packaging levels

On addressing the practical issues in the extraction of RLGC parameters for lossy multiconductor transmission lines using S-parameter models

Utilizing low loss dielectric material for high performance DRAM window-BGA design

Controlled impedance chip-to-chip interconnect using coplanar wire bond structures

A parameterized model order reduction technique for efficient solution of FEM eigenvalue problems

Fast reduced-order finite-element modeling of lossy coupled wires using lumped impedance elements

Thermal modeling of on-chip interconnects and 3D packaging using EM tools

An $H^{2}-matrix-based$ integral-equation solver of linear-complexity for large-scale full-wave modeling of 3D circuits

Time-domain orthogonal finite-element reduction-recovery (OrFE-RR) method for fast and accurate broadband simulation of die-package interaction

Proximity interconnect technology utilizing transmission line coupling for Stacked VLSI chips

AC coupled backplane communication using embedded capacitor

Computer code for fast macromodeling of large multiport systems

An over-12-Gbps on-chip transmission line interconnect with a pre-emphasis technique in 90 nm CMOS

Signal integrity improvement in transmission lines backed by an EBG structure

Signal integrity III

Minimizing crosstalk noise in vias or pins by optimizing signal assignment in a high-speed differential bus

Impedance design for multi-layered vias

Fewest vias design for microstrip guard trace by using overlying dielectric

Suppression of power/ground noise using differential vias

Multi-layer fringe-field augmentations for the efficient modeling of package power planes

Accuracy-preserving adaptive sampling of broadband electromagnetic spectra of interconnect structures

Chip-package co-simulation with multiscale structures

A methodology for incorporating metallization loss in the electromagnetic modeling of the power distribution network

Packaging modeling using fast broadband surface integral equation method

Special session/ tutorial

An industry-oriented curriculum in the design and performance of electrical packaging and interconnect

An end-to-end multi-GHz serial channel design process

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[1992 Proceedings] Electrical Performance of Electronic Packaging

A resonance-free power delivery system design methodology applying 3D optimized extended adaptive voltage positioning

Content Provider	IEEE Xplore Digital Library
Author	Tao Xu Brim, B.
Copyright Year	2008
Description	Author affiliation: Sigrity Inc., Santa Clara, CA (Tao Xu; Brim, B.)
Abstract	The extended adaptive voltage positioning (EAVP) method was applied to generate an initial decoupling capacitor (decap) design for a printed circuit board power delivery system (PDS). This initial design was tuned for maximum performance and minimum cost. A detailed 3D analysis of the PDS electrical behavior was first performed, then an automated optimization of decap selection and placement was applied. The PDS impedance of the final design was below 8 mOmega at all frequencies from DC to 2 GHz. A time domain verification of PDS noise performance was also examined.
Starting Page	107
Ending Page	110
File Size	480783
Page Count	4
File Format	PDF
ISBN	9781424428731
DOI	10.1109/EPEP.2008.4675889
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resonance Design optimization Voltage System analysis and design Power generation Capacitors Printed circuits Costs Performance analysis Impedance
Content Type	Text
Resource Type	Article

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