NDLI: Design and analysis of a TB/sec memory system

Content Provider	IEEE Xplore Digital Library
Author	Beyene, W.T. Madden, C. Namhoon Kim Hae-Chang Lee Perego, R. Secker, D. Yuan, C. Vaidyanath, A. Ken Chang
Copyright Year	2008
Description	Author affiliation: Rambus Inc., Los Altos, CA (Beyene, W.T.; Madden, C.; Namhoon Kim; Hae-Chang Lee; Perego, R.; Secker, D.; Yuan, C.; Vaidyanath, A.; Ken Chang)
Abstract	The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interface technology utilizes a bi-directional low-swing differential signaling with a data transfer rate of 16 Gbps/pair. The memory system uses asymmetrical architecture where the timing adjustment and equalization circuits for both memory WRITE and READ are on the controller to reduce the memory cost. This paper describes the design and analysis employed to develop the memory interface using conventional and low-cost interconnect technologies. The design and characterization of the prototype system at component and system-level are presented and model to hardware correlations are discussed at component and system levels. System analysis is used to optimize and predict the yield of the system, to calculate system timing and voltage margins, and to verify targeted bit-error-rate (BER).
Starting Page	21
Ending Page	24
File Size	13138106
Page Count	4
File Format	PDF
ISBN	9781424428731
DOI	10.1109/EPEP.2008.4675866
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Read-write memory Timing Bidirectional control Control systems Costs Integrated circuit interconnections Prototypes Hardware Voltage Bit error rate
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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