NDLI: High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

Content Provider	IEEE Xplore Digital Library
Author	Chunghyun Ryu Daehyun Chung Junho Lee Kwangyong Lee Taesung Oh Joungho Kim
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea (Chunghyun Ryu; Daehyun Chung; Junho Lee)
Abstract	In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circuit model is verified experimentally in frequency and time domains. Furthermore, the high frequency characteristics of the chip-to-chip vertical via are investigated.
Sponsorship	IEEE Microwave Theory and Techniques Soc. IEEE Components, Packaging and Manufacturing Technol. Soc
Starting Page	151
Ending Page	154
File Size	2234273
Page Count	4
File Format	PDF
ISBN	0780392205
DOI	10.1109/EPEP.2005.1563724
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Integrated circuit interconnections Stacking Packaging Silicon Equivalent circuits Semiconductor device measurement Coplanar waveguides Capacitance Scattering parameters
Content Type	Text
Resource Type	Article

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High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package