NDLI: EMI evaluation of a differential signaling interconnect at 3.2 Gbps

Content Provider	IEEE Xplore Digital Library
Author	Hao Shi Echevarria, V. Beyene, W.T. Xingchao Yuan
Copyright Year	2004
Description	Author affiliation: Rambus Inc., Los Altos, CA, USA (Hao Shi; Echevarria, V.; Beyene, W.T.; Xingchao Yuan)
Abstract	Differential signaling scheme has the inherent advantages of low electromagnetic interference (EMI) profile at multi-gigabits/s data rates. However, it is challenging to quantify the exact amount of EMI improvement due to the presence of other EMI sources in a realistic system. In this paper, we quantified the EMI benefit of a differential signaling system by using a test board characterized in a semianechoic chamber with pre-scan measurements. The test board contains an XDR/spl trade/ memory channel which uses differential signaling at 3.2 Gbps for data and single-ended signaling at 800 Mbps for command and address. It is measured in various operating modes and data patterns to differentiate the emissions from different sources such as clock nets, single ended signals, and differential signals. In addition, a near-field scanner is used to locate the EMI sources and/or antennas. The clock net is found to be the dominant source of EMI and the controller socket acted as the major EMI antenna. The high-speed differential data lines contribute to less than 1 dB of the overall EMI.
Sponsorship	IEEE Microwave Theory and Techniques Soc. IEEE Components, Packaging and Manufacturing Technol. Soc
Starting Page	65
Ending Page	68
File Size	3125851
Page Count	4
File Format	PDF
ISBN	0780392205
DOI	10.1109/EPEP.2005.1563702
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electromagnetic interference Antenna measurements Clocks Signal design Integrated circuit interconnections Communication system signaling System testing Communication system control Sockets Computer applications
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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