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2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014

2013 35th Electrical Overstress/Electrostatic Discharge Symposium

Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012

EOS/ESD Symposium Proceedings

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010

2009 31st EOS/ESD Symposium

EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium

2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

2006 Electrical Overstress/Electrostatic Discharge Symposium

2005 Electrical Overstress/Electrostatic Discharge Symposium

2004 Electrical Overstress/Electrostatic Discharge Symposium

2003 Electrical Overstress/Electrostatic Discharge Symposium

General chair's welcome

2003 EOS/ESD symposium steering committee

Table of contents

High performance IC package design and electrical reliability

A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies

Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies

Methods for designing low-leakage power supply clamps

Real-world charged board model (CBM) failures

A wafer level HBM tester delivering pulses with variable risetime through transmission lines

Transmission line pulsed photo emission microscopy as an ESD troubleshooting method

ESD protection design challenges for a high pin-count alpha microprocessor in a 0.13 μm CMOS SOI technology

TLP analysis of 0.125 μm CMOS ESD input protection circuit

Transient latch-up: Experimental analysis and device simulation

Characterization and modeling of transient device behavior under CDM ESD stress

Current filament movement and silicon melting in an ESD-robust DENMOS transistor

ESD phenomena in interconnect structures

Impact of layer thickness variations of SOI-wafer on ESD-robustness

High abstraction level permutational ESD concept analysis

On the development of passive/active guard electrode systems for human body electrostatic discharge (ESD) control

Advanced technology for monitoring plasma sparking ESD damage using high frequency magnetic field sensors

ESD sensitivity of devices on a charged printed wiring board

New methods for the assessment of ESD threats to electronic components

A physical model to explain electrostatic charging in an automotive environment; correlation with experimental approach

Characteristics of unipolar impulsive fields from a nearby ESD source

4.5GHz measurement of transition duration and frequency spectra due to small gap discharge as low voltage ESD

Real HBM & MM – the dV/dt threat

Comprehensive ESD protection for RF inputs

Co-design methodology to provide high ESD protection levels in the advanced RF circuits

ESD protection design for giga-Hz RF CMOS LNA with novel impedance-isolation technique

The effect of deep trench isolation, trench isolation and sub-collector doping on the electrostatic discharge (ESD) robustness of radio frequency (RF) ESD STI-bound P+/N-well diodes in BiCMOS silicon germanium technology

A study of vertical SiGe thyristor design and optimization

STMSCR: A new multi-finger SCR-based protection structure against ESD

Impact of elevated source drain architecture on ESD protection devices for a 90nm CMOS technology node

Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design

Creating and measuring photomask damage

Ion imbalances on the ionizer controlled work surface

Using electrostatic discharge test method for full characterization of dissipative and conductive materials

Flue gas cleaning using wet-type electrostatic precipitator

Biased-plate characterization of pulsed DC ionizers

Exploring a clean ESD laminate and ionic contamination methodology

Test procedures for predicting surface voltages on inhabited garments

All polymeric compounds: Conductive and dissipative polymers in ESD control materials

Coupled bipolar transistors as very robust ESD protection devices for automotive applications

Test circuits for fast and reliable assessment of CDM robustness of I/O stages

A traceable method for the arc-free characterization and modeling of CDM testers and pulse metrology chains

Capacitively coupled transmission line pulsing CC-TLP – A traceable and reproducible stress method in the CDM-domain

Combined TLP/RF testing system for detection of ESD failures in RF circuits

TLP systems with combined 50 and 500-ohm impedance probes and kelvin probes

Transmission line pulsed waveform shaping with microwave filters

Standardization of the transmission line pulse (TLP) methodology for electrostatic discharge (ESD)

ESD phenomena in GMR heads in the manufacturing process of HDD and GMR heads

A consideration about ionizer balance in HGA process

Continuous voltage monitoring techniques for improved ESD auditing

Study on magnetic instability of GMR heads using quasi static tester with laser heating function

ESD SPICE model and measurements for a hard disk drive

Wrist strap monitor testing for use with the latest MR head technologies

Effect of ESD transients on noise in GMR recording heads

Discharge current and electric field radiated from a small capacitance device

2003EOS/ESD symposium workshop and panel discussions

2002 ESD association outstanding contributions award

History of the EOS/ESD symposium

Mark your calender now and plan to attend!

2002 Electrical Overstress/Electrostatic Discharge Symposium

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1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

ESD SPICE model and measurements for a hard disk drive

Content Provider	IEEE Xplore Digital Library
Author	Wallash, A.
Copyright Year	2003
Description	Author affiliation: Maxtor Corp., Milpitas, CA, USA (Wallash, A.)
Abstract	A simple lumped RLC model for a hard disk drive is developed and used in SPICE circuit simulations. Simulation results were compared with experimental measurements using a special ldquohybridrdquo disk drive to validate the SPICE model. The voltage on and between the head and disk inside the drive were modeled during an ESD event to the baseplate and/or disk. Experimental measurements and SPICE modeling show that if the disk grounded when there is a large disk-to-base resistance, then head-to-disk electrical breakdown can occur. It is concluded that an electrical model is valuable in developing an understanding of the effects of ESD on a hard disk drive.
Starting Page	1
Ending Page	7
File Size	511786
Page Count	7
File Format	PDF
ISBN	9781585370573
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Electrostatic Discharge Association and Omnipress
Subject Keyword	Electrostatic discharge SPICE Hard disks Circuit simulation Disk drives Voltage Electrical resistance measurement Electric variables measurement Electric resistance Electric breakdown
Content Type	Text
Resource Type	Article

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