NDLI: 3D electro-thermal modeling of ggNMOS ESD protection structure

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The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

Volume 2 - 2004

Volume 1 - 2004

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems

Table of contents

Sessions schedule at a glace

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Message from the General Chair

Message from the Technical Program Chairs

International Steering Committee

Technical Program Committee

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The high walls have crumpled

Can shannon's channel capacity be challenged?

Strategies for high-tech academia uprising in 21 century

Design of OTA-C oscillators and current-mode filters using network transposition

A location system using asynchronous distributed sensors

Ear-type systems

The world of flatness

Technical sessions

A stable multi-level partitioning algorithm using adaptive connectivity threshold

Video coding algorithm based on adaptive tree for low electricity consumption

On the effectiveness of dynamically allocating resources across program execution phases for media workloads

A reconfigurable adaptive FEC system for reliable wireless communications

CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF

Booth memoryless modular multiplier with signed-digit number representation

High-speed VLSI design for Montgomery inverse over GF(2/sup m/)

Power aware design of an 8-bit pipelining asynchronous ANT-based CLA using data transition detection

An alternative scheme of redundant binary multiplier

Design of reconfigurable array multipliers and multiplier-accumulators

A speech codec with a class AB switch-current sigma-delta modulator and an area-efficient decimator/interpolator

A low voltage high unity-gain bandwidth CMOS op-amp

A multi-mode LDO-based Li-ion battery charger in 0.35/spl mu/m CMOS technology

Design of a high-transimpedance CMOS receiver for 600 Mb/s optical communications

A design of programmable AC voltage and current generators for testing energy meters

3D electro-thermal modeling of ggNMOS ESD protection structure

A Petri net based timing model for hardware/software co-design of digital systems

Accurate RT-level power estimation using up-down encoding

A distributed state variables approach to the transmission lines transient simulation

A multithreaded HDL simulator for deep submicron SoC designs

Lossless image compression via multi-scanning and adaptive linear prediction

Hadamard transform based fast codeword search algorithm for high-dimensional VQ encoding

A fast fractal image coding using pyramid structure of image blocks

Representation of 1/f signal via multiwavelet bases

A novel approach for image morphing

A 3.5GHz 2W MMIC power amplifier using AlGaAs/InGaAs/GaAs PHEMTs

High linearity power amplifier for PHS base station using a 50 mm AlGaAs/InGaAs/GaAs PHEMT

A 1V 2.4GHz CMOS power amplifier with integrated diode linearizer

Chip set design for 10GB/s optical transceiver

Design of a 12.8-Gb/s InP HBT limiting amplifier with cross-point control for driving a distributed modulator driver

A novel programmable digital signal processor for multimedia applications

A universal VLSI architecture for bit-parallel computation in GF(2/sup m/)

Efficient DSP architecture for Viterbi decoding with small trace back latency

A novel SOC architecture embedded bit serial FPGA

CDMA-based network-on-chip architecture

A bit-allocation model using on-line rate-distortion optimization in MPEG-4 rate control

A survey of error resilient coding schemes for image and video transmission based on data embedding

Implementation of half-pel motion estimation IP core for MPEG-4 ASP@L5 texture coding

Reconfigurable low power MPEG-4 texture decoder IP design

Rate control by partial differential equation modeling

Experimental evaluations of high-level energy optimization based on thread partitioning

A reusable methodology for non-slicing floorplanning

Zero-skew-clock algorithms for high performance system on a chip

An on-chip concurrent high frequency analog and digital sinusoidal generator

Efficient testing and design-for-testability schemes for multimedia cores: a case study on DCT circuits

An efficient speech enhancement method using filter and spectral subtraction

Improving G.728's hybrid window and excitation gain

Wavelet statistical model of speech for feature extraction and denoising

A computationally efficient noise estimation algorithm for speech enhancement

Fine granularity scalability for MP-CELP based speech coding with HPDR technique

Improving the clipped OFDM performance by using conic function

Design and simulation of a MIMO OFDM baseband transceiver for high throughput wireless LAN

A novel encoding/decoding technique of space-time block coded transceiver for IEEE 802.11a wireless local area network

An improved MIMO detector for high data rates wireless communications

Low power correlator of DSP core for communication system

Digital RDS demodulation in FM subcarrier systems

Laser/modulator driver with high modulation output operating up to 14-Gb/s using 0.35/spl mu/m SiGe BiCMOS process

Application of dual projected pseudo quasi Newton algorithm in multicommodity network flow problems

OC-48 generic frame mapping device for WAN accessing

A realization of diversity waveform sets for delay-Doppler imaging

Design of low-power switched-capacitor filter with switched-opamp technique

A low power and high-speed current latched comparator for weak current operations

Design techniques for low-voltage micropower CMOS switched-capacitor delta-sigma modulator

A sizing methodology for a low-noise comparator

A rail-to-rail, constant gain CMOS op-amp

A novel ultra-high speed signal capture based on a single FPGA chip

A CMOS infrared optical preamplifier with a variable-gain transimpedance amplifier

Design and analysis of a CMOS even harmonic mixer with current reuse circuits

A novel low noise design method for CMOS L-degeneration cascoded LNA

A 0.6V CMOS low noise amplifier for 2.4GHz application

An evaluation of SiGe/Si HBT high efficiency power amplifiers for wide dynamic power control range application

A fully integrated 5.2 GHz CMOS inductively degenerated low noise amplifier

A 1.5 V 2.4 GHz CMOS mixer with high linearity

A 2V CMOS low noise amplifier with tunable image filtering

Analysis of LO leakage due to LO mismatch in CMOS Gilbert mixer for direct conversion application

A low voltage 900 MHz voltage controlled ring oscillator with wide tuning range

A 1.8-V monolithic SiGe HBT power amplifier with a novel proposed linearizing bias circuit

Analysis of LO leakage in CMOS Gilbert mixer by cadence spectreRF for direct conversion application

An 1.25 Gbit/s -29 dBm burst-mode optical receiver realized with 0.35 /spl mu/m SiGe BiCMOS process using a PIN photodiode

Hardware design in statement level parallel processing

CMOS RF LNA with high ESD immunity

A 1 V 1.1 GHz CMOS integrated receiver front-end

Analysis and improvement on propagation efficiency of high-speed asymmetric differential transmission system

Performance trade-offs in designing a dual-band CMOS IEEE 802.11A/B frontend

Symbol-spaced delay circuit design with half-rate clock timing for multi-taps FIR filter as pre-emphasis

An ultra low-power output feedback flip-flop

0.75-V subthreshold CMOS logic using dynamic substrate bias

Leakage current reduction in CMOS logic circuits

Two efficient area reduction methods for implementations of the Rijndael advanced encryption standard

A chaos-based fully digital 120 MHz pseudo random number generator

A module generator for parameterized DSP core

Digital signal processor architectures and programming

Real-time 3D image computation using LUT-based DSP systems

A low-cost and application-driven digital signal processor for speech/audio processing

A new RNS to mixed-radix number converter using modulo (2/sup p/ - 1) signed-digit arithmetic

A variable-length DHT-based FFT/IFFT processor for VDSL/ADSL systems

Spatial correlation of a circular array antenna and BER performance investigation

Baseband transceiver design for the DVB-terrestrial standard

Design of partially adaptive STBC CDMA receiver using conjugate gradient algorithm

Design of common structures for CDMA systems

Efficient weighted L/sub P/ algorithm for the design of low-pass FIR filters with some closed-form derivations

Design and application of variable fractional order differentiator

A design method of multi-channel cyclic filter banks with less multiplications by genetic algorithm

Dedicated structure for tunable multiband FIR filters with linear phase and maximally flat magnitude

Design of 2D FIR digital filters with symmetric properties by genetic algorithm approach

A low jitter phase-lock loop based on a new adaptive bandwidth controller

A new LC-tank voltage controlled oscillator

Design of a dual-band 5/2.4 GHz CMOS VCO for 802.11 A/B/G WLAN transceivers

A 1-V 2.4-GHz CMOS frequency synthesizer with current-match charge pump

Handover considerations in VCO design for multistandard wireless receiver

Design of a system-on-chip for ECG signal processing

Complexity-aware design of a DA-based FIR filters

A new dynamic scaling FFT processor

A maskable memory architecture for rank-order filtering

Low-error carry-free fixed-width multipliers and their application to DCT/IDCT

A novel BIB-based parallel download scheme

Network planning and capacity management considering adaptive sectorization in survivable FDMA/CDMA systems

Improving RPR fairness convergence

Optimizing one-to-one data communication on double-loop networks

System optimization of contents delivery network with information-zooming function

Adaptive receivers with PN code tracking for DS-CDMA communications

Simultaneous bidirectional PAM-6 wired link with adaptive pre-emphasis and trellis coding

Performance bounds for block transmission system

A new technique for digital compensation in IQ modulator

Determination of bandwidth and free spectral range for the silicon based ring resonators and racetrack microcavity resonators

A new variable step size method for the LMS adaptive filter

Adaptive two-stage LQ reliable control of uncertain discrete-time systems

Adaptive lowpass filters

Sound minimisation for local active control

Optimal design of stable recursive digital filters using unconstrained optimization methods

Removing operation of empty rooms on sequence-pair

Moment computations for R(L)C interconnects with multiple resistor loops using ROBDD techniques

Iterative convergence of optimal wire sizing and available buffer insertion for zero-skew clock tree optimization

Clock period minimization method of semi-synchronous circuits by delay insertion

DTA: layout design tool for CMOS analog circuit

Modified Euler path rule for MOS layout minimization

Assignment constrained scheduling under max/min logic/interconnect delays for placed datapath

Modeling and simulation of phase-locked loop with Verilog-A description for top-down design

Circuit schematic generation and optimization in VLSI circuits

An optimization approach for SoC FSM verification

Bus-oriented DFT design for embedded cores

Automatic protocol translation and template based interface synthesis for IP reuse in SoC

Simulation model and soft commutation strategy for current-fed matrix converter

Design and realization of personal computer-based continuous passive motion device to prevent shoulder joint stiffness

High-speed sense amplifier for SRAM applications

H/sub /spl infin// sliding mode tracking control for Chua's circuit

Estimating good local cross sections of expansive flow

Adaptive DWT-based watermarking scheme using neighboring mean value relationship

A trellis-enhanced secure spread watermarking scheme and its performance analysis

Seal imprint verification with rotation invariance

Optimization of multi-purpose watermarking algorithm

Fast multiple reference frame selection method for motion estimation in JVT/H.264

A novel predict hexagon search algorithm for fast block motion estimation on H.264 video coding

Low complexity variable-size block-matching motion estimation for adaptive motion compensation block size in H.264

VLSI architecture design for variable-size block motion estimation in MPEG-4 AVC/H.264

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3D electro-thermal modeling of ggNMOS ESD protection structure

Content Provider	IEEE Xplore Digital Library
Author	Haolu Xie Rouying Zhan Wang, A. Gafiteanu, R.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA (Haolu Xie; Rouying Zhan; Wang, A.; Gafiteanu, R.)
Abstract	This work presents a simple-to-implement, 3D electro-thermal model for circuit-level SPICE simulation of grounded-gate NMOS (ggNMOS), with application for ESD (electrostatic discharge) protection circuit design verification. A new ESD discharging fitting resistor (R/sub on/) is employed to improve ESD electrical modeling in the high-current region and a new 3D thermal resistor parameter (R/sub th/) is proposed to model the electro-thermal characteristics of ggNMOS. The extraction method for the new parameters, R/sub on/ and R/sub th/, is discussed. Finally, simulation results are presented and compared with experimental data.
Starting Page	61
Ending Page	64
File Size	235151
Page Count	4
File Format	PDF
ISBN	0780386604
DOI	10.1109/APCCAS.2004.1412691
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-12-06
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrostatic discharge Protection SPICE Electric breakdown Thermal resistance Breakdown voltage Circuit simulation MOS devices Circuit synthesis Resistors
Content Type	Text
Resource Type	Article

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