NDLI: A.2 CDM at the nanoscale frontier

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2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

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2013 35th Electrical Overstress/Electrostatic Discharge Symposium

Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012

EOS/ESD Symposium Proceedings

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010

2009 31st EOS/ESD Symposium

EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium

2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

2006 Electrical Overstress/Electrostatic Discharge Symposium

General Chair's Welcome

Table of contents

System event triggered latch-up in IC chips: test issues and chip level protection design

A new mechanism for core device failure during CDM ESD events

ESD damage due to HBM stressing of non-connected pins

HBM stress of no-connect IC pins and subsequent arc-over events that lead to human-metal-discharge-like events into unstressed neighbor pins

Novel technique to reduce latch-up risk due to ESD protection devices in Smart Power technologies

Turn-off characteristics of the CMOS snapback ESD protection devices - new insights and its implications

Characterization and modeling of three CMOS diode structures in the CDM to HBM timeframe

ESD protection considerations in advanced high-voltage technologies for automotive

Dual-direction Isolated NMOS-SCR device for system level ESD protection

Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced Smart Power technology

ESD protection for high-voltage CMOS technologies

Operation analysis and implementation of CMOS compatible vertical bipolar ESD protection devices for automotive applications

A study of ESD protection for helical-scan tape heads

ESD induced instability of Pinned layer in GMR head

Study on EMI phenomena for GMR/TMR head

Breakdown evaluation of ultrathin barrier magnetic tunnel junctions with V-Ramp testing

A resistive ferrite substrate for the GMR head in helical-scan tape systems

Effect of electrostatic discharge on tunneling magnetoresistive sensor

Thermal characteristics of a PtMn GMR sensor subjected to square wave EOS pulses

A new electrical overstress (EOS) test for magnetic recording heads

Relations between system level ESD and (vf-)TLP

Cable discharges into communication interfaces

Radiated ESD noise of 5 GHz-band from walkers

EMI power measurements of ESD radiated fields

Partially Depleted SOI body-contacted MOSFET-triggered silicon controlled rectifier for ESD protection

Concept for body coupling in SOI MOS transistors to improve multi-finger triggering

Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection

Comprehensive ESD protection for flip-chip products in a dual gate oxide 65nm CMOS technology

An active ESD protection technique for the power domain boundary in a deep submicron IC

ESD protection design for mixed-power domains in 90nm CMOS with new efficient power clamp and GND current trigger (GCT) technique

Tunable bipolar transistor for ESD protection of HV CMOS applications

High voltage ESD protection strategies for USB and PCI applications for 180nm/130nm/90nm CMOS technologies

A novel ionizer design With both DC and AC high voltage bias

Development of ion balance sensor by using MOSFET

Trends in external ionizer monitoring and control

Ionization applications and pitfalls for charge neutralization in substrate handling

Is CO2 bubbling (carbonation) a requirement at semiconductor wafer sawing process

Solution of destructive separation charge generation

Voltage dependence of spark resistance at low voltage ESD in air and reed switch

Analysis of the triggering behavior of low voltage BCD single and multi-finger gc-NMOS ESD protection devices

Ultra-thin gate oxide reliability in the ESD time domain

Transmission line pulse (TLP) testing of radio frequency (RF) micro-machined micro-electromechanical systems (MEMS) switches

Transient analysis of ESD protection elements by time domain transmission using repetitive pulses

Using coupled lines to produce highly efficient square pulses for VF-TLP

A frequency-domain VFTLP pulse characterization methodology and its application to CDM ESD modeling

Pre Pulse Voltage in the Human Body Model

Methods to remove anomalies from human body model pulse generators

Different CDM ESD Simulators provide different failure thresholds from the same device even though all the simulators meet the CDM standard specifications

HBM tester parasitic effects on high pin count devices with multiple power and ground pins

ESD control and design for extremely sensitive ("Class 0") devices

A.2 CDM at the nanoscale frontier

ESD troubleshooting and testing practices

Automated ESD rule verification & EDA tools

Controlling ESD in automated process equipment

Advanced topics in ESD auditing

System level stress and the impact on device ESD protection

Layout for ESD and latchup robustness

Cleanrooms/ESD/lonization guidelines and considerations

ESD protection considerations in high voltage technologies

Outstanding contribution award

2006 Exhibitors list

History of the EOS/ESD symposium

[Future events]

2005 Electrical Overstress/Electrostatic Discharge Symposium

2004 Electrical Overstress/Electrostatic Discharge Symposium

2003 Electrical Overstress/Electrostatic Discharge Symposium

2002 Electrical Overstress/Electrostatic Discharge Symposium

2001 Electrical Overstress/Electrostatic Discharge Symposium

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)

Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396)

Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347)

Proceedings Electrical Overstress/Electrostatic Discharge Symposium

1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

A.2 CDM at the nanoscale frontier

Content Provider	IEEE Xplore Digital Library
Copyright Year	2006
Abstract	Summary form only given, as follows. A record of the workshop was not made available for publication as part of the conference proceedings. This workshop will explore the CDM ESD effects from different perspectives that now challenge the robustness of semiconductor products. 1) Technology scaling: How do new processes, materials and device structures affect CDM sensitivity? Can new process, devices, or circuit techniques be developed to counteract these increasing sensitivities? 2) Application performance challenges: How will the challenges of complex chip integration and mixed signal circuit blocks be overcome? What are the protection / performance tradeoffs for RF and ultra-high speed serial communications links? 3) Chip-level & packaging design issues: What challenges are faced in integrating multiple voltage domains, mixed signal elements, RF circuits in a digital chip? How does packaging affect CDM performance, and can package design be optimized for improved CDM protection? 4) CDM qualifications: Will the industry need to lower its expectations of on-chip protection, and place more emphasis on reducing ESD exposure on the manufacturing floor? Are our CDM test methods even representative of real world CDM stresses? You are also invited to send your comments to the workshop moderator at info@esda.org, with the topic "2006 ESD Symposium Workshop" in the subject line.
Starting Page	365
Ending Page	365
File Size	146211
Page Count	1
File Format	PDF
ISBN	9781585371150
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	EOS/ESD Association, Inc.
Subject Keyword	Electrostatic discharge Circuits Protection Packaging Radio frequency Earth Observing System Nanoscale devices Robustness Semiconductor materials Signal design
Content Type	Text
Resource Type	Article

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