NDLI: Input-output-buffered ATM switches with delayed backpressure mechanisms

Content Provider	IEEE Xplore Digital Library
Author	Badran, H.F. Mouftah, H.T.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Queen's Univ., Kingston, Ont., Canada (Badran, H.F.; Mouftah, H.T.)
Abstract	This paper presents a study of the effect of the delay in the back-pressure signal in an architecture with input-output-buffering with back-pressure control, on the switch performance. The exact value of the delay depends on the specific implementation of the back-pressure mechanism and the contention resolution policy. This involves the mechanism by which the information is broadcasted to the input ports. The study demonstrates that the delay in the back-pressure signal seriously affects the switch performance, since it could result in severe cell loss at the output ports. This cell loss at the output ports can be controlled by modifying the output queue management mechanism, i.e. by incorporating additional buffering at the output ports on top of the original output queue size. The amount of this additional buffering depends on the value of the delay in the back-pressure signal, and it does not seriously affect the size of the input buffers. Higher values of delay in the back-pressure signal do not adversely affect the cell loss at the input ports. This study also investigates the overall input and output buffer allocation policies to achieve acceptable cell loss performance for architectures with delayed back-pressure mechanisms.<>
Starting Page	771
Ending Page	774
File Size	457475
Page Count	4
File Format	PDF
ISBN	0780324161
DOI	10.1109/CCECE.1993.332410
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-09-14
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Asynchronous transfer mode Switches Delay effects Performance loss Output feedback Broadcasting Centralized control Pressure control Signal resolution Size control
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Buffer size trade-offs in input/output buffered ATM switches under various conditions

Head of line arbitration in ATM switches with input-output buffering and backpressure control

Performance of input-buffered and output-buffered ATM switches under bursty traffic: simulation study

Performance analysis of nonblocking multi-plane ATM switches with input/output buffers and priorities

Closed loop credit-based flow control with internal backpressure in input and output queued switches

Output buffered ATM switch with frame discard

Performance analysis of ATM switch fabric with combined-input/output buffering

Performance evaluation of input buffered ATM switch architectures: throughout, delay and packet loss analyses

A performance model of space-division ATM switches with input and output queueing

Input-output-buffered ATM switches with delayed backpressure mechanisms

Similar Documents

Buffer size trade-offs in input/output buffered ATM switches under various conditions

Head of line arbitration in ATM switches with input-output buffering and backpressure control

Performance of input-buffered and output-buffered ATM switches under bursty traffic: simulation study

Performance analysis of nonblocking multi-plane ATM switches with input/output buffers and priorities

Closed loop credit-based flow control with internal backpressure in input and output queued switches

Output buffered ATM switch with frame discard

Performance analysis of ATM switch fabric with combined-input/output buffering

Performance evaluation of input buffered ATM switch architectures: throughout, delay and packet loss analyses

A performance model of space-division ATM switches with input and output queueing

Input-output-buffered ATM switches with delayed backpressure mechanisms