NDLI: Low power programmable front-end for a multichannel neural recording interface

Content Provider	IEEE Xplore Digital Library
Author	Gosselin, B. Simard, V. Sawan, M.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada (Gosselin, B.; Simard, V.; Sawan, M.)
Abstract	In this paper a programmable gain preamplification front-end for a fully implantable multichannel data acquisition system (IMDAS) that is dedicated for chronic neural signal recording is proposed. This application calls for very low power and low voltage circuit techniques. To satisfy these constraints, the preamplifier is designed in 0.18 /spl mu/m CMOS technology and all employed transistors operate in weak inversion. To maximize the dynamic range of the recorded signals, the preamplifier's gain is set by a 4-bit digital-to-analog converter (DAC). This DAC is used to tune the bias currents of a variable transconductor cell in order to vary its DC gain. The simulation of the whole proposed module gives a maximum power consumption of 530 nW at a supply voltage of 0.9 V. The circuit provides a maximum gain of 47 dB, has a cutoff frequency of 2.65 KHz and presents an input-referred noise of 7.65 /spl mu/Vrms which is sufficiently low to meet the required precision. In addition, the phase margin is higher than 50/spl deg/ on the entire gain range.
Starting Page	911
Ending Page	914
File Size	251068
Page Count	4
File Format	PDF
ISBN	0780377818
ISSN	08407789
DOI	10.1109/CCECE.2003.1226042
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-05-04
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Preamplifiers CMOS technology Data acquisition Low voltage Dynamic range Digital-analog conversion Transconductors Circuit simulation Energy consumption Gain
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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