NDLI: Implementation of DSP-RAM: an architecture for parallel digital signal processing in memory

Content Provider	IEEE Xplore Digital Library
Author	Kwan, B.S.-H. Cockburn, B.F. Elliott, D.G.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada (Kwan, B.S.-H.)
Abstract	We describe a synthesizable implementation in VHDL of a parallel architecture for signal processing called DSP-RAM. DSP-RAM is an enhanced version of the earlier computational RAM (C-RAM) architecture proposed by Elliott (see Ph.D. thesis, Dept.of Electrical Engineering, University of Toronto, Canada, 1998). Like C-RAM, the new architecture integrates on the same chip both memory storage and single instruction stream, multiple data stream parallel data processing. Unlike in C-RAM, each processing element contains a multiplier-accumulator that can directly handle 16-bit data words; in contrast, C-RAM is organized to perform massively-parallel, bit-serial computation. The VHDL DSP-RAM model was verified by simulating three promising applications: FIR digital filtering, the discrete cosine transform (DCT), and vector quantization (VQ). A controller circuit along with a simple micro-programming language were also designed to facilitate the implementation of applications.
Sponsorship	Gen. Electr. Company
Starting Page	341
Ending Page	345
File Size	529752
Page Count	5
File Format	PDF
ISBN	0780367154
ISSN	08407789
DOI	10.1109/CCECE.2001.933707
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-13
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Finite impulse response filter Discrete cosine transforms Signal synthesis Parallel architectures Signal processing Read-write memory Random access memory Data processing Computational modeling
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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