NDLI: Design of a high performance pipelined transversal filter for fading channels equalization

Content Provider	IEEE Xplore Digital Library
Author	Wassal, A.G. Hasan, M.A.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada (Wassal, A.G.)
Abstract	A transversal filter with variable tap-gains is designed using a pipelined transposed architecture. An adaptive equalizer could be easily designed using this filter to mitigate distortion and provide diversity for mobile applications in time-varying fading channels. Also, different architectures for the implementation of the multipliers and the adders were compared with respect to the delay and area. The carry look-ahead with carry select was the architecture of choice for the adders and the Booth-coded Wallace tree architecture for the multipliers. The filter was implemented using an ASIC CMOS technology with a minimum feature of 0.5 /spl mu/m and the simulation results proved the design to be correctly functioning at frequencies up to 120 MHz with the power dissipation estimated to be around 756 mW. The chip can operate at much higher frequencies by making use of the state-of-the-art CMOS and packaging technologies.
Starting Page	213
Ending Page	215
File Size	340944
Page Count	3
File Format	PDF
ISBN	078034314X
ISSN	08407789
DOI	10.1109/CCECE.1998.682720
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-25
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transversal filters CMOS technology Frequency estimation Adaptive equalizers Adaptive filters Fading Delay Application specific integrated circuits Power dissipation Packaging
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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