NDLI: Development Flow for FPGA-Based Scalable Reconfigurable Systems

Content Provider	IEEE Xplore Digital Library
Author	Caba, J. Dondo, J.D. Rincon, F. Barba, J. Lopez, J.C.
Copyright Year	2013
Description	Author affiliation: Dept. of Technol. & Inf. Syst., Univ. of Castilla-La Mancha, Ciudad Real, Spain (Caba, J.; Dondo, J.D.; Rincon, F.; Barba, J.; Lopez, J.C.)
Abstract	Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, for instance we can change a part of the initial functionality after its deployment, where a complete configuration is not needed, and the total area required is reduced. However, the design of partially reconfigurable systems has been a complex task yet. This work try to facilitate the design process and proposes a new development flow, which reduces mistakes during first stages of the design and makes the building of partial reconfiguration projects easier. In addition, we provide a dedicated hardware component, which manages bit streams nd dynamic areas. This component speed up the reconfiguration time, accomplishing a speed about 180MB/s.
Starting Page	666
Ending Page	669
File Size	263836
Page Count	4
File Format	PDF
ISBN	9781479929788
DOI	10.1109/DSD.2013.129
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Software Hardware Complexity theory Layout Production facilities Engines Field-Programmable Gate Array Dynamic Partial Reconfiguration Design Flow
Content Type	Text
Resource Type	Article

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