NDLI: Digital Late-Transition Metastability Simulation Model

Content Provider	IEEE Xplore Digital Library
Author	Polzer, T. Steininger, A.
Copyright Year	2013
Description	Author affiliation: Inst. of Comput. Eng., Vienna Univ. of Technol., Vienna, Austria (Polzer, T.; Steininger, A.)
Abstract	As modern systems-on-chip contain increasingly more clock domain crossings, the associated metastability effects become much more pronounced. To maintain the reliability of the design, efficient means for metastability analysis become mandatory. We propose an approach that allows simulation of late transitions, the most dominant effect of metastability in modern VLSI chips. While this approach is purely digital and hence very fast, it allows a precise treatment in the time domain. These properties make it attractive for modeling even complex circuit structures. The core of our approach is a timing model that carefully maps the relative times of setting the latch opaque and the arrival of new data at the input to the appropriate data-input/output delay. Unlike with existing models this mapping is not simply linear and hence restricted to a very narrow scope, it rather works for arbitrary inter-arrival times between data and enable. We systematically elaborate an analytic description of this input/output delay and illustrate how the respective model parameters can be derived from an initial circuit simulation, either automatically or with manual support. Once calibrated, the model allows fast and precise simulation, which we illustrate in a case study.
Starting Page	121
Ending Page	128
File Size	218993
Page Count	8
File Format	PDF
ISBN	9781479929788
DOI	10.1109/DSD.2013.21
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mathematical model Integrated circuit modeling Tin Latches Equations Delays Computational modeling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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