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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Molina, M.C. Mendias, J.M. Hermida, R. |
| Copyright Year | 2002 |
| Description | Author affiliation: Dept. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain (Molina, M.C.; Mendias, J.M.; Hermida, R.) |
| Abstract | This paper proposes an allocation algorithm able to perform the combined resource selection and operation binding of multiple-precision specifications that maximizes the bit-level reuse of hardware resources. Additionally, it presents an analytic method to estimate the amount of area that our approach could save in comparison with traditional allocation algorithms. In order to minimize the cost of the implementations obtained, the proposed algorithm produces circuits only influenced by the maximum number of bits calculated per cycle. This approach contrasts with the cost of implementations designed by traditional algorithms, which also depends on the number and widths of the operations executed in every cycle. |
| Starting Page | 385 |
| Ending Page | 392 |
| File Size | 473863 |
| Page Count | 8 |
| File Format | |
| ISBN | 0769517900 |
| DOI | 10.1109/DSD.2002.1115396 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-09-04 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware High level synthesis Algorithm design and analysis Costs Circuits Resource management Delay High performance computing Computational efficiency Design methodology |
| Content Type | Text |
| Resource Type | Article |
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