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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Drechsler, R. Gunther, W. Eschbach, T. Linhard, L. Angst, G. |
| Copyright Year | 2002 |
| Description | Author affiliation: Inst. of Comput. Sci., Bremen Univ., Germany (Drechsler, R.) |
| Abstract | In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a new recursive bi-partitioning algorithm that is especially applicable, if a large number of final partitions, e.g. more than 1000, has to be computed. The algorithm consists of two steps. Based on recursive splits the problem is divided into several sub-problems, but with increasing recursion depth more run time is invested. By this an initial solution is determined very fast. The core of the method is a second step, where a very powerful greedy algorithm is applied to refine the partitions. Experimental results are given that compare the new approach to state-of-the-art tools. The experiments show that the new approach outperforms the standard techniques with respect to run time and quality. Furthermore, the memory usage is very low and is reduced in comparison to other methods by more than a factor of four. |
| Starting Page | 38 |
| Ending Page | 44 |
| File Size | 378610 |
| Page Count | 7 |
| File Format | |
| ISBN | 0769517900 |
| DOI | 10.1109/DSD.2002.1115349 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-09-04 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Partitioning algorithms Computer science Very large scale integration Field programmable gate arrays Algorithm design and analysis Application software Greedy algorithms Design automation Design optimization Routing |
| Content Type | Text |
| Resource Type | Article |
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