NDLI: Evaluation of delay fault testability of LUT functions for improved efficiency of FPGA testing

Content Provider	IEEE Xplore Digital Library
Author	Krasniewski, A.
Copyright Year	2001
Description	Author affiliation: Inst. of Telecommun., Warsaw Univ. of Technol., Poland (Krasniewski, A.)
Abstract	Testing delay faults in FPGAs differs significantly from testing delay faults in circuits whose combinational sections can be represented as gate networks. Based on delay fault testability conditions, formulated in a form suitable for analysis of LUT-based FPGAs, we develop an original method for the evaluation of delay fault testability of LUT functions. It relies on an indicator called delay fault activation profile. The proposed method supports an analysis and comparison of different procedures for the enhancement of detectability of FPGA delay faults that rely on transformations of user-defined functions of LUTs in the combinational logic block under test. We demonstrate the effectiveness of our method by applying it to prove the efficiency and to optimize a specific procedure for the transformation of LUT functions which preserves the blocking capability and input-output transition pattern of original functions.
Sponsorship	Euromicro
Starting Page	310
Ending Page	317
File Size	815671
Page Count	8
File Format	PDF
ISBN	0769512399
DOI	10.1109/DSD.2001.952312
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-04
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Table lookup Field programmable gate arrays Circuit faults Circuit testing Automatic testing Fault detection Built-in self-test Integrated circuit interconnections Delay estimation Logic testing
Content Type	Text
Resource Type	Article

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