NDLI: Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning

Content Provider	IEEE Xplore Digital Library
Author	Zhiyuan He Zebo Peng Eles, P.
Copyright Year	2006
Description	Author affiliation: Embedded Syst. Lab., Linkoping Univ. (Zhiyuan He; Zebo Peng; Eles, P.)
Abstract	This paper presents a test scheduling approach for system-on-chip production tests with peak-power constraints. An abort-on-first-fail test approach is assumed, whereby the test is terminated as soon as the first fault is detected. Defect probabilities of individual cores are used to guide the test scheduling and the peak-power constraint is considered in order to limit the test concurrency. Test set partitioning is used to divide a test set into several test sequences so that they can be tightly packed into the two-dimensional space of power and time. The partitioning of test sets is integrated into the test scheduling process. A heuristic has been developed to find an efficient test schedule which leads to reduced expected test time. Experimental results have shown the efficiency of the proposed test scheduling approach
Starting Page	1
Ending Page	6
File Size	476295
Page Count	6
File Format	PDF
ISBN	3981080114
DOI	10.1109/DATE.2006.244141
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-06
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	System testing System-on-a-chip Production systems Fault detection Concurrent computing
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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